case study on 8086

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8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to 1MB storage. It consists of powerful instruction set, which provides operations like multiplication and division easily.

It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor.

Features of 8086

The most prominent features of a 8086 microprocessor are as follows −

It has an instruction queue, which is capable of storing six instruction bytes from the memory resulting in faster processing.

It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in faster processing.

It is available in 3 versions based on the frequency of operation −

8086 → 5MHz

8086-2 → 8MHz

It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance.

Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.

Execute stage executes these instructions.

It has 256 vectored interrupts.

It consists of 29,000 transistors.

Comparison between 8085 & 8086 Microprocessor

Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.

Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.

Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.

Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction queue.

Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a pipelined architecture.

I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.

Cost − The cost of 8085 is low whereas that of 8086 is high.

Architecture of 8086

The following diagram depicts the architecture of a 8086 Microprocessor −

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The unlikely child born of the home computer wars, recent posts.

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Optimizing for the 8088 and 8086 CPU, Part 3: A Case Study In Speed

Posted by Trixter on January 18, 2013

In this final part of 8088 optimization posts , I present a case study for 8088 optimization. Specifically, I’ll cover a problem that I needed to solve, how I solved it, how long it took to optimize my solution for 8088, and what the performance benefit was from that optimization.

For the TL;DR crowd who will likely skip to the end of the article: Through clever 8088 optimization and a thorough understanding of our problem, a decompression routine was created that not only beats all known methods previously created for 8088 , but can actually exceed the speed of a memcopy given the right input. But to see how this was achieved, you’ll have to grab a snack and settle down for 10 minutes.

Now, on with our case study.

My interest in speed optimization stems from being a lifelong fan of the demoscene . I’ve written some productions and unleashed a few cheap tricks here and there, but my core strength has actually been “glue” — understanding the underlying hardware and marrying the code to it. For example, while I coded a few effects in Explicit , my core role was actually assembling the demo itself — the timer/interrupt system, the music library, the 3D library, asset management, decompression, debugging, event handling, etc. all fell to me. And that’s fine, I enjoy doing it. (Next time you run Explicit, hold down the ALT key and you’ll see some realtime debug stats overlayed onscreen while the demo is running.) So this is why I tend to write the underlying framework of a demo before actually writing the individual effects, because if the framework is solid, the rest is “easy”. To me, anyway.

For many years, I’ve been threatening to write a proper demo for the 8088. 8088+CGA has been done a few times back in the day by Sourcerers , and there was a nice slideshow+music demo done for the Tandy 1000 as part of the 8086 compo , but there really hasn’t been a proper demo for the 8088 — 3D, graphics hardware tricks, nice design, the works. Every year I get closer, writing another piece of something that will eventually turn into a demo. A month ago, that piece turned out to be a need for fast decompression. (What I am going to use fast decompression for is left as an exercise for the democoder!) And by fast, I mean fast enough to be considered transparent: The user/programmer should not be aware that the decompression step took any time at all. Democoder parlance for this is “realtime” decompression.

So, a proper definition of the problem we’re trying to solve would be:

We need to store data on disk in a form that takes up less space than its normal working state (ie. compression must actually occur — you can’t shrink 16 bytes out of a 64KB file and then call it a day)
To be useful for most situations, we must be able to decompress the data with a minimum of work for the programmer (ie. one simple call with no special preparation or preexisting state required)
Decompression must be fast enough to be considered transparent to the programmer (ie. take not much more time than a straight copy of the uncompressed data would)

For that last stipulation to be quantifiable, we need to decide what “fast enough” is. For our purposes, we will define “fast enough” to be roughly 4x slower than a straight memory copy (which 8088/8086 implements as a REP MOVSW). That kind of speed is respectable on any platform, so this seems like a fair starting point to gauge our progress.

The (de)Compression Method

So, what compression format will we write a decompression routine for? What formats lend themselves to fast decompression? What formats are even possible to decompress on our lowly 8088 with RAM that is measured in kilobytes instead of gigabytes? The answer, it turns out, is obvious — but only if you know what to look for. Like compression itself, we have to take a long time researching our problem before coming to a short conclusion.

A Quick Primer

Before picking a compression format to use, I will offer this extremely short primer to readers unfamilar with compression basics, so that the rest of the article will make sense. If you’re already familiar with what compression is, skip this part.

For our purposes, compression is the process of removing the redundancy out of a file so that it consists of only the unique parts and not the repeated or redundant parts. Consider this sentence:

She sells seashells by the seashore. (36 characters)

You can see that both “sells” and “seashells” share a sequence of letters (“ells “), as does “seashells” and “seashore” (“seash”). If we notice this and assign a custom code to both pieces (ie. AA =”ells ” and BB =”seash”), and then replace those portions of the sentence with the codes, we can shorten the space the sentence takes up:

She s AABBAA by the BB ore. (24 characters)

Was actual compression achieved? Yes, because while the codes and what they represent take up space, we got to use them twice each. A code takes up two characters, but it represents five characters. So the sentence+codes take up 24 characters in compressed form, and the code definitions take up 10 more characters, so our total space usage is 34 characters compared to the original 36.

Saving two characters is nothing to write home about, but that was a single sentence. When you extend the idea to an entire novel, you begin to see how the coded sequences can get used more and more often until you have real space savings on your hands. We only used our codes twice, but across an entire novel, and combined with other codes, they’ll get used thousands of times, saving bytes here and there each time.

A Quick Primer (For Programmers)

There are many ways to compress data but the fastest methods are almost universally based on LZ77 . LZ77 produces a compressed format that boils down to two types of sequences:

Data that must be inserted directly into the target buffer (because we couldn’t find smaller ways to represent it), called LITERALS
Data we already have somewhere that can be copied into the target buffer, called MATCHES

In our quest for high-speed decompression, we will only be considering LZ77-style compression methods. Not only are they fast to decode, but they’re also very easy to understand.

Again, the above is oversimplified for our purposes. For an excellent write-up on compression methods for low-resource platforms such as 8-bit CPUs, consult Pasi Ojala’s pucrunch page .

What To Compare Against

If you asked most DOS users in the early 1990s what the fastest compression/decompression software was, most of them would likely answer PKZIP. PKZIP was popular precisely because of its speed and reasonably good compression, and was so popular that it’s a format much of the world still uses more than 20 years later. PKWare released a Data Compression Library (DCL) of assembler-optimized routines for compression and decompression in 1991 for commercial use, which perform at roughly the same speed and ratio as PKZIP.

If this library exists, why are we bothering to write our own decompression routine? Why not just use the DCL for our needs? We’re writing our own because we want to explore what the state of the art can be for the 8088, and also because we aren’t sure what the state of the art actually is. Since the DCL was considered by many to be the best overall solution in terms of compression ratio and speed, that is the benchmark we will compare ourselves to. (It also helps that the DCL’s execution speed can be exactly timed just like we will be timing our code — more on timing later in this article.) In other words, if we can beat the DCL, we must be doing well.

(Compression nerds like myself may point out that the DCL uses Implode rather than PKZIP’s DEFLATE , but the two are nearly identical so I feel it is a fair comparison to use the DCL.)

The Current State Of The Art

There are many high-speed compression/decompression open-source libraries in use today. The oldest one still in wide use is UCL , written in the mid 1990s; there are newer ones written in the last five years that routinely compete for the top speed spot, such as QuickLZ , Snappy , and LZ4 . My original idea was to examine all four of these to see what made the most sense to implement on the 8088. UCL was appealing because it had assembler code already written for the 8088/8086 as part of the library, but it was full of conditional branches and bit shifting/isolation, something the 8088 just isn’t very good at; there is also no published UCL data format (as far as I could find) so if I ran into issues, I’d likely be out of luck. QuickLZ is C code that assumes the underlying architecture is 32-bit or better, so while I could have written a decompression routine for QuickLZ data, it would have involved a lot of 32-bit memory values, adding to the complexity of the implementation. So both of these were out pretty quickly.

Snappy is Google’s library, and it looked very promising, mostly because it was implemented the way I would have written my own compression format: Simple code expansion, variable lengths, codes that are packed into data aligned by bytes. Source and format are fully documented , easy to understand, and in use by Google. No real downsides, right?

Snappy was going to be my first choice, but then I researched LZ4 . As soon as I saw LZ4, I knew immediately it was the correct choice for the 8088 and got very excited. Not only was it the right choice for ease of implementation on 8088, but a unique design decision for the format lent itself to speed that I hadn’t seen before. Here’s what got me so excited:

Interleaved literal-match structure : This is the innovative discovery of LZ4. Yann Collet (the author of LZ4) realized that all compressed LZ77 data consisted of both literal runs and match runs, so rather than try to devise complicated codes that branch based on run type, he organzied the format so that there are always literals, then matches, then literals, then matches, etc. repeating until the end of the compressed data. This eliminates a lot of literal/matchcode-based branching. There are really only three branches ever required for decompressing LZ4: Two length calculations (and only if they’re needed), and a check to see if we’re out of codes to expand. Those three are the only major conditional branches! This is REALLY HUGE and is why LZ4 is at the top of the speed charts for nearly every platform.

64KB window size, 16-bit offsets : A 64K window size means that decompressing LZ4 doesn’t need any special handling — if you only have 64K to decompress (likely on our platform), you don’t have to worry about switching segments after the first 64K. And a 16-bit offset is a single word read, no unpacking. It’s like LZ4 was specifically created for Intel memory models , but it wasn’t — it was actually created in the very early 1990s for Yann’s HP48 calculator, which used a CPU based on nybbles. Which explains the code packing in the next advantage:

Simple codes : The literal lengths and match lengths are, if 14 or lower, stored as two nybbles in the same byte. That means both can be read with a single byte read and then cached as necessary. Even if the lengths are larger than 14, it only takes a few byte reads to get the full length. No wacky code unpacking like LZS or higher LZO levels.

No setup : All it takes to decompress one buffer into another is both buffers — no hash tables to initialize, no dictionary to load or build, no need to know the length of the decompressed size beforehand, etc.

Optimal Parsing : This is the secret sauce. It has nothing to do with how we will write our decompression routine, but it does have to do with decent compression ratios. And also speed, because LZ77-style compression schemes decompress in mostly linear time. Meaning, the smaller a file is, the faster it will decompress (ie. there is less actual work to do). LZ4_HC is the LZ4 variant that will take as much time as it needs to find the absolute perfect representation of the source data given the supplied encoding, and it is included in the LZ4 library and example programs.

All of the above makes LZ4 a winner for our architecture. But is it a winner for our workflow? If LZ4 was proprietary and difficult to use, that could be a problem. With stable vetted code, a BSD license, and Windows and Linux binaries for the compressor, it is a good fit for most cross-development workflows. (Most modern hobbyist retroprogramming is cross-development, with only speed-sensitive code requiring the actual hardware for testing.)

I’m not the only one to come to this conclusion; LZ4 is finding its way into tons of things from Apache Hadoop to Solaris kernels . Buy Yann a beer the next time you see him.

A Naive Implementation

Starting with only the format description and format diagram, I was able to code up a naive but functional decompressor in about half an hour in assembly. Normally I would have written it up in a HLL first to make sure my understanding was sound, but the format was so simple I thought that assembly would have been just as fast to code, and it was. I won’t reproduce 200 lines of assembler code here (a link to the finished code will come later), but it might help to know how I organized the routine:

DS:SI – Location of compressed data (the source) ES:DI – Location of decompressed data (the target) AX – scratch BX – translation table CX – loops, literal/match run lengths DX – “cache” for literal and match length token BP – size of compressed data (so we know when to stop!)

Here is what compressed LZ4 data looks like:

Yes, it really is this simple, which means you should be able to code up a naive implementation just from looking at the above diagram and reading the format explanation .

Assume Nothing!

The #1 suggestion I can give anyone trying to optimize code has nothing to do with either assembler or the 8088: Benchmark, benchmark, benchmark. Know exactly how fast your code runs on the hardware you are targeting . If you don’t, you don’t have a basis for comparison and are flying blind when you optimize.

Following my own advice, I wrote a test harness for the decompression code and linked it with a modified version of Michael Abrash’s Zen Timer , which gives nearly perfect microsecond timing of sections of code using the 8253 PIT built into (or emulated in) every PC. I then created a variety of “test subjects” to run through the decompressor, and made sure the test harness compared the output of the routine with the original source material to verify it wasn’t getting mangled on output. I chose three typical files to do most of my timing with — “typical” in that they were the most likely things I would be decompressing: Compiled code, plain-English text, and a hand-drawn CGA picture. Each had their strengths and weaknesses and provided different stresses to the routine: The picture had a lot of large matches, the text had a lot of small matches, and the binary didn’t have much of either. The picture also had a lot of “runs” where a single value was repeated. Measuring with the Zen Timer, all three datatypes took a total of 530434 microseconds (usecs), or 0.53 seconds, to decompress.

After checking the output was correct for my test data, I then proceeded to write a harness for PKWare’s DCL that did the same thing: Compressed all three test subjects into its own format, then decompressed all three to memory and recorded the decompression time. While I knew the DCL traded some size for speed, it was still the fastest general-purpose algorithm in use at the time so I was expecting some real competition. To my surprise, the DCL took 7.75 seconds to decompress the test data — over 14 times slower!

Thoroughly satisfied, I almost stopped right there, as my goal of beating the DCL was already accomplished. But I just couldn’t help thinking what a proper optimization would do, and exactly how both perform on more different types of data (was my sample size too small?), so I decided to go through with the optimization exercise anyway.

Chapter 27, In Which It Blows Up In My Face

I’m not going to cover every optimization in meticulous detail, because that would likely lose what few readers have made it to this point. However, one optimization attempt deserves special attention for the fact that it uncovered a bug in all Intel x86 CPUs made through the 80286, and illustrates the importance of having a proper test harness for your code.

Looking closer at how I chose to copy matched data around in the ES:DI destination buffer, it seemed wasteful to preserve DS, point DS to the match, then restore DS when I was only copying a handful of bytes in some cases. Most memory operations on 8088 can take a segment override, even the string operations in some cases, so with a single prefix you can turn this:

…to this:

So, I got rid of the DS setup/restore code, changed REP MOVSB to REP ES: MOVSB, and patted myself on the back. Imagine my horror when a test run showed the output buffer had entire chunks that were either incorrect or in the wrong place . Worse, on a subsequent run, it was still wrong but in different places! I spent hours single-stepping through the code in a debugger, looking for things like uninitialized registers or incorrect compressed data. Finding nothing wrong, I then spent another hour testing my hard disk and RAM to see if my 30-yr-old IBM 5160 was finally starting to die.

Finding nothing, and noting that the code worked if I reverted my changes, I looked at REP ES: MOVSB and wondered if I was encoding it improperly. So I switched the order of the prefixes to ES: REP MOVSB. This resulted in the jaw-dropping result of mangling the entire output buffer . What the hell was going on?

With some research, and clarification from Robert Wessel on comp.lang.asm.x86, I confirmed that all CPUs from the 8086 through the 80286 have a bug where returning from an interrupt only resumes the most recent prefix, not both. So after an interrupt, a REP ES: MOVSB continues as ES: MOVSB which copies a single byte and then stops. My second attempt made things worse, as an interrupted ES: REP MOVSB continues as REP MOVSB which, without the ES: override, copies data from the wrong location!

One way to fix this is to disable interrupts before you run that code, then re-enable when done, but I didn’t want to do that because you never know if someone will need interrupts to run while decompression is occuring. (I know I do, anyway.) I decided to work around the problem like this:

With a fix in place, and valid output confirmed, I timed the code. After all that heartache, I found that the overall routine slowed down by 8209 cycles, because the ES: override adds two cycles to every byte copy. The entire concept was a bust, so I reverted the code.

This just goes to show you why timing your code is important. In your head or on paper, some optimizations can seem like a win, but conditions outside your understanding or control can affect the final result.

It’s Obvious

Some optimizations, using the information provided in part 1 and part 2 of this guide, were easy to implement and usually didn’t result in a lot of code shuffling around. Here’s an abbreviated table of what was done and how many cycles it saved. (Remember, the three test cases took roughly 500000 usec to execute, so every 5000 usecs saved is 1% shaved off the execution time.)

Not everything I touched turned to gold. Here is a summary of optimization attempts that failed and were subsequently rolled back:

Eliminating a “nothing to do” check (turns out the check-and-jump saved us some time after all)
Eliminating the REP MOVSW optimization f0r literal copies (I thought the special handling wasted time, but the MOVSW gains are worth the trouble)
Handling very short literal lengths manually with individual MOV’s (as opposed to letting REP MOVS do it)
Handling very short match lengths manually with individual ES: MOVSW statements (as opposed to letting the REP MOVS do it)

With 43390 usecs saved, I was a man possessed: I wanted to speed it up further, but had run out of 8088 tricks. The only way I was going to continue on this journey was to gain further insight into the data I was dealing with, so I wrote an LZ4 data analyzer.

Not So Obvious

One of my favorite quotes from Zen of Assembly: “The best optimizer is between yours ears.” It alludes to dumb/blind optimization — what I was doing up until this point, working like a human peephole optimizer — being inferior to “smart” optimization, where you analyze the problem itself to come up with different ways to solve it.

I had made some assumptions about the structure and frequency of LZ4 data, so to confirm those assumptions, I wrote a simple program to walk through my compressed sample set and print out some stats: What the shortest lengths were, the longest, the averages, and anything else that might give me some ideas. Some sample output:

====== robotron.lz4 Compressed size: 21040 Decompressed size: 40704 ===== Literals: Minimum: 0 Average: 3 Maximum: 385 Total: 11336 # of events: 3139 Matches: Minimum: 4 Average: 9 Maximum: 512 Total: 28634 # of events: 3098 1-byte runs: Minimum: 4 Average: 31 Maximum: 217 Total: 593 # of events: 19 2-byte runs: Minimum: 4 Average: 6 Maximum: 14 Total: 141 # of events: 21

Looking at various outputs, I was struck by how many match offsets of 1 and 2 there were. Offsets that small, with lengths larger than the offsets, essentially translate into RLE sequences . LZ77 code usually deals with this by just copying the same bytes over and over, but x86 architecture has a string opcode that can do this more efficiently: REP STOS. Put a value into AL or AX, a count into CX, and off you go, filling memory with that value until the count runs out. What is especially notable about STOS is that it is faster than every other instruction for putting a value in memory , faster than even a raw REP MOVSW copy. So if you can use it, you can exceed memcopy speeds for short sections. Adding special handling for offsets of 1 and 2 and redirecting them to special-case code that used STOS resulted in a larger-than-expected 32281 usec savings all by itself — that’s the largest single savings out of all the attempts — and it also resulted in a special surprise which I’ll cover later.

After I ran out of ideas looking at the analyzer output, on a hunch I looked a the LZ4 format description a second time and noticed that, by design, the last five bytes are always literals. The current structure of the code would check for this exit condition, then process matches, then jump to the next token and continue. By unrolling some code to move the “are we done?” test to the end of the loop instead of the middle, I was able to combine both the test and the loop jump into a single instruction. This saved cycles every iteration, leading to the second largest savings at 10946 usecs.

The analyzer also confirmed some of my suspicions, such as most lengths were 14 or less and would rarely need to jump to the “build a longer length” section of the code. By structuring the code such that the most common cases “fell through”, I was saving cycles each iteration.

So, when all was said and done, what was our time savings?

After all of the above work (which incidentally took about ten hours of free time spread out over a few weeks), we managed to take an already fast routine and shave 95856 usecs from it — an 18% improvement from the already fast routine where we started. Was 18% worth the effort? I definitely think so. It may not sound like much, but think about the savings like this: If a user would wait a full minute for decompression of a lot of data to finish, they now only have to wait 50 seconds. What was a 5-minute task now only takes 4 minutes. (And believe me, on an 8088, it wasn’t uncommon to be sitting in front of the machine waiting 5 minutes for something to finish.)

But that’s not the end of the story. Looking at more varied data than our three test subjects, we make an astonishing discovery (lower numbers are better):

For data that has a lot of 1-byte and 2-byte runs — runs that we specifically catch and handle with REP STOSW, as noted previously — we see that decompression exceeds REP MOVSW copy time . It is actually faster to decompress such data than it is to merely copy it . That is crazy.

I’m still smug from the speed victory over the DCL, so let’s kick it while it’s down and compare its speed to ours (lower numbers are better):

Now, all this doesn’t mean anything if the actual compression LZ4 provides is horrible. Thanks to optimal parsing, it’s not — in fact, compared to the DCL’s Implode, it’s extremely close. LZ4 and Implode differ by only a few percentage points:

Conclusion and Downloads

Hopefully I’ve illustrated why optimization can be worth the effort. Having transparant decompression can solve a lot of problems in any program that has to manage a lot of assets. And maybe I’m crazy, but I found it extremely fun to see just how much blood I could squeeze from a stone.

Can the routine be sped up further? It can, actually, but doing so would require a lot of additional work on the part of the programmer (such as storing the compressed data on the stack and using POP to retrieve data). I also toyed with the idea of translating the LZ4 compressed data into a slightly different format that was more optimal to parse, but some quick tests showed that the transformed data is slightly larger as a result, which resulted in more data to read, which took up more time than the cycles saved by a more efficient implementation. About the only thing I can think of is that it might make sense to build literal/match lengths using REP SCASW looking for a word that wasn’t FFFF, but only if you knew had large lengths beforehand in your compressed data, which is unlikely.

So, as is, I believe this to be the very fastest implementation of LZ4 decompression possible on an 8088 CPU. All this in 436 bytes of compiled code (180 for the code and 256 for a translation table), and without requiring the programmer to jump through hoops to use it. This was a blast.

All code, binaries, and examples are available under what I’m calling the DSL (Demoscene License) so leech away . I’ve also made two versions of the Zen Timer available; an older package that extends support to C and Turbo Pascal, and a newer package that drops TP support but adds 32-bit protected mode C compiler support. Both packages have a “long timer” mode that can time periods larger than 54ms, albeit with a hair of jitter due to background interrupt noise.

Now, anyone want to help teach me fast 3D? This demo won’t write itself, ya know.

22 Responses to “Optimizing for the 8088 and 8086 CPU, Part 3: A Case Study In Speed”

Peter Ferrie said

Quick question, not really relevant, anymore, but is JCXZ next ; continue if REP completed LOOP @again ; keep trying if REP never completed next:

faster than INC CX ; compensate for LOOP effect LOOP @again ; keep trying if REP never completed ?

Trixter said

Your second example is faster, but it doesn’t do the same thing as the former. If the REP completes, CX will be 0, whereas your INC CX will roll it around to FFFF and the loop will start over and run for the maximum.

I responded to your private email, and some of your suggestions did increase speed, so there will be a second release of the code soon :-)

you don’t have the jcxz in the second case. @again: rep … inc cx loop @again if the rep completed, cx will be zero, inc->cx=1, loop->cx=0 again and fall through. if the rep did not complete, then inc->cx=cx+1, loop->cx=cx-1, and it continues from @again with the correct count.

Ah, I see what you mean. Yes, that would work and saves 5 cycles from eliminating the JCXZ fall-through, and INC CX is a single-byte instruction. I can’t time this right now but I’m pretty sure it’s a win in both speed and size. Nice :-)

Krister Nordvall said

No, that would not work. Peter’s code would return to the string instruction with CX unchanged as opposed to your code which returns with CX decremented by 1.

Thanks for a very interesting article!

Andrew Jenner said

This is completely awesome and I can’t wait to make some stuff to compress with it! Seriously impressive results.

I definitely want to help teach you fast 3D. Have you read my blog post about deriving the equations for 3D graphics ( http://www.reenigne.org/blog/equations-for-3d-graphics )? I think after that it’s mostly just a question of optimization by massive application of lookup tables, the exact set of lookup tables you use depending on just what kind of effect you’re doing.

Then there’s the question of drawing points, lines and triangles quickly, which is a whole other optimization problem. I’ve played about a little with some of these routines and there’s lots of interesting optimizations that can be done there too.

I hadn’t seen your post, but I just now read it, and I think the lightbulb started to flicker a little. When I decide to set aside a few weeks and dedicate myself to the task, I’ll show you what I’ve got and maybe we can take it from there. I have seen all sorts of tricks like multiplication via quarter-square method, performing less calcs if not rotating by all three axis, storing vertices in clockwise order to help with culling and rendering, etc. but I only have partial understanding of those methods.

Drawing points and lines and filling a scanline quickly — that I’ve got down pat, no worries there.

reenigne said

My most recent blog post is about the quarter-square method! http://www.reenigne.org/blog/multiplying-faster-with-squares/

Normally you do rotations by multiplying a 3-element vector with a 3×3 matrix, which is 9 multiplications. However, if you only rotate about two axes you can get a guaranteed zero in one of the matrix elements, which takes you down to 8 multiplications per vertex. If you can exploit some symmetries in the model you’re drawing you can probably get it down even further.

Given three 2D points A, B and C in a 2D space, there’s a really easy way to tell visiting the points in the order A, B, C has you going clockwise or anticlockwise – it’s just the sign of the cross product of the vectors AB and AC. That orientation corresponds to whether the triangle that you’re drawing is facing towards or away from you (assuming that the order is the same for all your triangles – clockwise is just a convention). Obviously that only helps if you want to draw only one side of each triangle, for example if you’re drawing a solid object – if you’re drawing a thin surface then it doesn’t help because you need to draw both sides of each triangle anyway.

Knowing that (and that you can use the same “orientation” method to figure out if a point is inside or outside a triangle) was actually what got me my first job I think – it certainly seemed to impress the interviewer, as it was a better solution than the one he knew!

I knew I had quarter-square multiplication on the brain from somewhere!

the included lz4.exe creates a header of 16 bytes in length, rather than 8, which of course can’t be decompressed with the existing code.

I realised this morning that it’s the result of non-stream mode. the command-line in compress.bat is necessary to avoid that problem. I should have read the documentation.

Terje Mathisen said

I liked the final part of your optimization effort, up to that point your code must have been _very_ similar to my first attempt. :-)

Detecting one and two-byte match loops that could be turned into rep stos was a very nice idea!

Coming from you, that means very much to me, thanks!

I started looking at a 32-bit asm version and wondered if I could find a better way to handle match strings that could be turned into REP STOS:

The idea is that I can turn 1-byte RLE into 2-byte by simply duplicating the last byte in the output buffer, and I can turn 2-byte into 4-byte if I start by duplicating the last word!

; EDX has match offset, ECX count (>= 4), EBX = EDI-EDX

cmp edx, 2 jb do_stosb je do_stosw

cmp edx,4 je do_stosd

; Use REP MOVS to copy the (possibly overlapping) range do_movs: lea edx,[ebx+ecx] xchg ebx,esi ; Save ESI and point it at match source cmp edx,edi ja overlapping_range

mov edx,ecx shr ecx,2 and edx,3 rep movsd mov ecx,edx

overlapping_range: rep movsb mov esi,ebx jmp start_literal

do_stosb: ; Duplicate the last byte mov al,[ebx] mov [edi],al

do_stosw: ; Duplicate the last word mov ax,[ebx] mov [ebx+2],ax

do_stosd: xor edx,edx mov eax,[ebx] ; All four bytes will be valid! sub edx,ecx add ecx,3 and edx,3 shr ecx,2 rep stosd sub edi,edx

start_literal:

Nice! You’ve saved me the work if I ever move up to 32-bit prot mode (unlikely, as I’m still exploring what 8088 can do, but never say never)

mov ax,[ebx] mov [ebx+2],ax you’d save two bytes by using eax in both cases.

Loading EAX would be safe, but writing EAX to [ebx+2] could write 5 bytes past the current end of the output buffer…

This is still fine, since LZ4 always ends with a literal, so even if this is the last match and it is just 4 bytes long, the extra byte will be overwritten by the final copy.

OTOH, using AX doubles the chances of avoiding misaligned load and/or store operations.

Excellent work and a great post. I love reading blog articles that took some effort, not just a link to somewhere else. Thanks!

I was thinking about this earlier today – instead of xlat, why not aam 10h? CPU performs ah=al>>4 and al&=0fh for you. of course, I haven’t checked the compatibility (does it exist on the NEC?) or the timings, but it seems like it would be an improvement for some code paths, at least. it also frees bx for bp replacement.

Doesn’t work on NEC V20/V30, and is almost an order of magnitude slower than XLAT (AAM on 808x takes 83 cycles).

ricardoquesada said

thanks. the 3 parts were a great read!

Quite welcome. In the next year or so, there might be a new series of 8088 optimization articles.

Microprocessor Tutorial

8086 pins configuration

The description of the pins of 8086 is as follows:

AD0-AD15 (Address Data Bus): Bidirectional address/data lines. These are low order address bus. They are multiplexed with data.

When these lines are used to transmit memory address, the symbol A is used instead of AD, for example, A0- A15.

A16 - A19 (Output): High order address lines. These are multiplexed with status signals.

A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals S3 and S4.

A18/S5: A18 is multiplexed with interrupt status S5.

A19/S6: A19 is multiplexed with status signal S6.

BHE /S7 (Output): Bus High Enable/Status. During T1, it is low. It enables the data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE signal. It is multiplexed with status signal S7. S7 signal is available during T3 and T4.

RD (Read): For read operation. It is an output signal. It is active when LOW.

Ready (Input): The addressed memory or I/O sends acknowledgment through this pin. When HIGH, it denotes that the peripheral is ready to transfer data.

RESET (Input): System reset. The signal is active HIGH.

CLK (input): Clock 5, 8 or 10 MHz.

INTR: Interrupt Request.

NMI (Input): Non-maskable interrupt request.

TEST (Input): Wait for test control. When LOW the microprocessor continues execution otherwise waits.

VCC: Power supply +5V dc.

GND: Ground.

Operating Modes of 8086

There are two operating modes of operation for Intel 8086, namely the minimum mode and the maximum mode .

When only one 8086 CPU is to be used in a microprocessor system, the 8086 is used in the Minimum mode of operation.

In a multiprocessor system 8086 operates in the Maximum mode .

Pin Description for Minimum Mode

In this minimum mode of operation, the pin MN/ MX is connected to 5V D.C. supply i.e. MN/ MX = VCC.

The description about the pins from 24 to 31 for the minimum mode is as follows:

INTA (Output): Pin number 24 interrupts acknowledgement. On receiving interrupt signal, the processor issues an interrupt acknowledgment signal. It is active LOW.

ALE (Output): Pin no. 25. Address latch enable. It goes HIGH during T1. The microprocessor 8086 sends this signal to latch the address into the Intel 8282/8283 latch.

DEN (Output): Pin no. 26. Data Enable. When Intel 8287/8286 octal bus transceiver is used this signal. It is active LOW.

DT/ R (output): Pin No. 27 data Transmit/Receives. When Intel 8287/8286 octal bus transceiver is used this signal controls the direction of data flow through the transceiver. When it is HIGH, data is sent out. When it is LOW, data is received.

M/ IO (Output): Pin no. 28, Memory or I/O access. When this signal is HIGH, the CPU wants to access memory. When this signal is LOW, the CPU wants to access I/O device.

WR (Output): Pin no. 29, Write. When this signal is LOW, the CPU performs memory or I/O write operation.

HLDA (Output): Pin no. 30, Hold Acknowledgment. It is sent by the processor when it receives HOLD signal. It is active HIGH signal. When HOLD is removed HLDA goes LOW.

HOLD (Input): Pin no. 31, Hold. When another device in microcomputer system wants to use the address and data bus, it sends HOLD request to CPU through this pin. It is an active HIGH signal.

Pin Description for Maximum Mode

In the maximum mode of operation, the pin MN/�MX is made LOW. It is grounded. The description about the pins from 24 to 31 is as follows:

QS1, QS0 (Output): Pin numbers 24, 25, Instruction Queue Status. Logics are given below:

S0 , S1 , S2 (Output): Pin numbers 26, 27, 28 Status Signals. These signals are connected to the bus controller of Intel 8288. This bus controller generates memory and I/O access control signals. Logics for status signal are given below:

LOCK (Output): Pin no. 29. It is an active LOW signal. When this signal is LOW, all interrupts are masked and no HOLD request is granted. In a multiprocessor system all other processors are informed through this signal that they should not ask the CPU for relinquishing the bus control.

RG / GT1 , RQ / GT0 (Bidirectional): Pin numbers 30, 31, Local Bus Priority Control. Other processors ask the CPU by these lines to release the local bus.

In the maximum mode of operation signals WR , ALE, DEN , DT/ R etc. are not available directly from the processor. These signals are available from the controller 8288.

Functional units of 8086

8086 contains two independent functional units: a Bus Interface Unit (BIU) and an Execution Unit (EU) .

Fig: Block Diagram of Intel 8086 Microprocessor (8086 Architecture)

Bus Interface Unit (BIU)

The segment registers, instruction pointer and 6-byte instruction queue are associated with the bus interface unit (BIU).

Handles transfer of data and addresses,
Fetches instruction codes, stores fetched instruction codes in first-in-first-out register set called a queue ,
Reads data from memory and I/O devices,
Writes data to memory and I/O devices,
It relocates addresses of operands since it gets un-relocated operand addresses from EU. The EU tells the BIU from where to fetch instructions or where to read data.

It has the following functional parts:

Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next instruction and stores them in the instruction queue and this process is known as instruction pre fetch. This process increases the speed of the processor.
Code Segment Register (CS): Code segment of the memory holds instruction codes of a program.
Data Segment Register (DS): The data, variables and constants given in the program are held in the data segment of the memory.
Stack Segment Register (SS): Stack segment holds addresses and data of subroutines. It also holds the contents of registers and memory locations given in PUSH instruction.
Extra Segment Register (ES): Extra segment holds the destination addresses of some data of certain string instructions.
Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor acts as a program counter. It indicates to the address of the next instruction to be executed.

Execution Unit (EU)

The EU receives opcode of an instruction from the queue, decodes it and then executes it. While Execution, unit decodes or executes an instruction, then the BIU fetches instruction codes from the memory and stores them in the queue.
The BIU and EU operate in parallel independently. This makes processing faster.
General purpose registers, stack pointer, base pointer and index registers, ALU, flag registers (FLAGS), instruction decoder and timing and control unit constitute execution unit (EU). Let's discuss them:
General Purpose Registers: There are four 16-bit general purpose registers: AX (Accumulator Register), BX (Base Register), CX (Counter) and DX. Each of these 16-bit registers are further subdivided into 8-bit registers as shown below:
Stack Pointer (SP)
Base Pointer (BP)
Source Index (SI)
Destination Index (DI)
ALU: It handles all arithmetic and logical operations. Such as addition, subtraction, multiplication, division, AND, OR, NOT operations.
Auxiliary Flag
Parity Flag
Overflow Flag
Interrupt Flag
Direction Flag

Interrupt is a process of creating a temporary halt during program execution and allows peripheral devices to access the microprocessor.

Microprocessor responds to these interrupts with an interrupt service routine (ISR) , which is a short program or subroutine to instruct the microprocessor on how to handle the interrupt.

There are different types of interrupt in 8086:

Hardware Interrupts

Hardware interrupts are that type of interrupt which are caused by any peripheral device by sending a signal through a specified pin to the microprocessor.

The Intel 8086 has two hardware interrupt pins:

NMI (Non-Maskbale Interrupt)
INTR (Interrupt Request) Maskable Interrupt.

NMI: NMI is a single Non-Maskable Interrupt having higher priority than the maskable interrupt.

It cannot be disabled (masked) by user using software.
It is used by the processor to handle emergency conditions. For example: It can be used to save program and data in case of power failure. An external electronic circuitry is used to detect power failure, and to send an interrupt signal to 8086 through NMI line.

INTR: The INTR is a maskable interrupt. It can be enabled/disabled using interrupt flag (IF). After receiving INTR from external device, the 8086 acknowledges through INTA signal.

It executes two consecutive interrupt acknowledge bus cycles.

Software Interrupt

A microprocessor can also be interrupted by internal abnormal conditions such as overflow; division by zero; etc. A programmer can also interrupt microprocessor by inserting INT instruction at the desired point in the program while debugging a program. Such an interrupt is called a software interrupt.

The interrupt caused by an internal abnormal conditions also came under the heading of software interrupt.

Example of software interrupts are:

TYPE 0 (division by zero)
TYPE 1 (single step execution for debugging a program)
TYPE 2 represents NMI (power failure condition)
TYPE 3 (break point interrupt)
TYPE 4 (overflow interrupt)

Interrupt pointer table for 8086

Fig: Interrupt pointer table for 8086

The 8086 can handle up to 256, hardware and software interrupts.

1KB memory acts as a table to contain interrupt vectors (or interrupt pointers), and it is called interrupt vector table or interrupt pointer table. The 256 interrupt pointers have been numbered from 0 to 255 (FF hex). The number assigned to an interrupt pointer is known as type of that interrupt. For example, Type 0, Type 1, Type 2,...........Type 255 interrupt.

Addressing modes of 8086

The way for which an operand is specified for an instruction in the accumulator, in a general purpose register or in memory location, is called addressing mode .

The 8086 microprocessors have 8 addressing modes. Two addressing modes have been provided for instructions which operate on register or immediate data.

These two addressing modes are:

Register Addressing: In register addressing, the operand is placed in one of the 16-bit or 8-bit general purpose registers.

Immediate Addressing: In immediate addressing, the operand is specified in the instruction itself.

MOV AL, 35H
MOV BX, 0301H
MOV [0401], 3598H
ADD AX, 4836H

The remaining 6 addressing modes specify the location of an operand which is placed in a memory.

These 6 addressing modes are:

Direct Addressing: In direct addressing mode, the operand?s offset is given in the instruction as an 8-bit or 16-bit displacement element.

ADD AL, [0301]

The instruction adds the content of the offset address 0301 to AL. the operand is placed at the given offset (0301) within the data segment DS.

Register Indirect Addressing: The operand's offset is placed in any one of the registers BX, BP, SI or DI as specified in the instruction.

MOV AX, [BX]

It moves the contents of memory locations addressed by the register BX to the register AX.

Based Addressing: The operand's offset is the sum of an 8-bit or 16-bit displacement and the contents of the base register BX or BP. BX is used as base register for data segment, and the BP is used as a base register for stack segment.

Effective address (Offset) = [BX + 8-bit or 16-bit displacement].

MOV AL, [BX+05]; an example of 8-bit displacement.
MOV AL, [BX + 1346H]; example of 16-bit displacement.

Indexed Addressing: The offset of an operand is the sum of the content of an index register SI or DI and an 8-bit or 16-bit displacement.

Offset (Effective Address) = [SI or DI + 8-bit or 16-bit displacement]

MOV AX, [SI + 05]; 8-bit displacement.
MOV AX, [SI + 1528H]; 16-bit displacement.

Based Indexed Addressing: The offset of operand is the sum of the content of a base register BX or BP and an index register SI or DI.

Effective Address (Offset) = [BX or BP] + [SI or DI]

Here, BX is used for a base register for data segment, and BP is used as a base register for stack segment.

ADD AX, [BX + SI]
MOV CX, [BX + SI]

Based Indexed with Displacement: In this mode of addressing, the operand's offset is given by:

Effective Address (Offset) = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement

MOV AX, [BX + SI + 05]; 8-bit displacement
MOV AX, [BX + SI + 1235H]; 16-bit displacement

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A specification of the intel 8085 microprocessor: A case study

Part III Rapid Prototyping With Algebraic Specification
Conference paper
First Online: 01 January 2005
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Alfons Geser 1

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 394))

Included in the following conference series:

Workshop on Algebraic Methods

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4 Citations

As an instance for a large specification, an algebraic specification of the intel 8085 micro-processor is given. The specification is based on the concepts of hierarchical abstract types and conditional equations. With the help of the specification interpreter RAP, the specification is validated against some of its informal requirements. In the design of large software systems, a number of informal specification properties have to be considered such as style, readability, and structuredness of a specification. These properties are talked about using a couple of small examples.

Machine Instruction
Abstract Data Type
Algebraic Specification
Specification Interpreter
Conditional Jump

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

intel is a registered trademark of intel Corporation, Santa Clara, CA.

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Geser, A. (1989). A specification of the intel 8085 microprocessor: A case study. In: Wirsing, M., Bergstra, J.A. (eds) Algebraic Methods: Theory, Tools and Applications. Algebraic Methods 1987. Lecture Notes in Computer Science, vol 394. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0015045

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Microprocessor Tutorials

Introduction

Introduction of Microprocessor
Types of Microprocessors
Microprocessor | Intel x86 evolution and main features
Evolution of Microprocessors

8085 Microprocessor

Architecture of 8085 microprocessor.

Pin diagram of 8085 microprocessor
Registers of 8085 microprocessor
Flag register in 8085 microprocessor
Addressing modes in 8085 microprocessor
Data transfer instructions in 8085 microprocessor
Arithmetic instructions in 8085 microprocessor
Logical instructions in 8085 microprocessor
Branching instructions in 8085 microprocessor
Timing diagram of MOV Instruction in Microprocessor

8085 Programs

8085 program to add two 8 bit numbers
8085 program to add three 16 bit numbers stored in registers
8085 program to add 2-BCD numbers
8085 program to subtract two 8-bit numbers with or without borrow
8085 program to divide two 16 bit numbers
8085 program to find the factorial of a number
8085 program to generate Fibonacci series
8085 program to swap two 16 bit numbers using Direct addressing mode
8085 program to add numbers in an array
8085 program for bubble sort
Assembly language program to find largest number in an array
8085 program to reverse 16 bit number
8085 code to convert binary number to ASCII code
8085 program to find 1’s and 2’s complement of 16-bit number
8085 program to check whether the given number is even or odd
8085 program to find square of a 8 bit number
8085 program to find smallest number between two numbers
8085 program to find maximum and minimum of 10 numbers

8086 Microprocessor

Architecture of 8086
Pin diagram of 8086 microprocessor
General purpose registers in 8086 microprocessor
Flag register of 8086 microprocessor
Addressing modes in 8086 microprocessor
Arithmetic instructions in 8086 microprocessor
Logical instructions in 8086 microprocessor
Data transfer instructions in 8086 microprocessor
Process control instructions in 8086 microprocessor
String manipulation instructions in 8086 microprocessor
Program execution transfer instructions in 8086 microprocessor
Reset Accumulator (8085 & 8086 microprocessor)
Difference between CALL and JUMP instructions
Interrupts in 8086 microprocessor

8086 Programs

8086 program to add two 16-bit numbers with or without carry
8086 program to add two 16 bit BCD numbers with carry
8086 program to subtract two 16 bit BCD numbers
8086 program to multiply two 16-bit numbers
8086 program to find sum of Even numbers in a given series
8086 program to find sum of odd numbers in a given series
8086 program to find average of n numbers
8086 program to find the factorial of a number
8086 program to find Square Root of a number

Introduction :

The 8085 microprocessor is an 8-bit microprocessor that was developed by Intel in the mid-1970s . It was widely used in the early days of personal computing and was a popular choice for hobbyists and enthusiasts due to its simplicity and ease of use. The architecture of the 8085 microprocessor consists of several key components, including the accumulator, registers, program counter, stack pointer, instruction register, flags register, data bus, address bus, and control bus.

The accumulator is an 8-bit register that is used to store arithmetic and logical results. It is the most commonly used register in the 8085 microprocessor and is used to perform arithmetic and logical operations such as addition, subtraction, and bitwise operations.

The 8085 microprocessor has six general-purpose registers, including B, C, D, E, H, and L, which can be combined to form 16-bit register pairs. The B and C registers can be combined to form the BC register pair, the D and E registers can be combined to form the DE register pair, and the H and L registers can be combined to form the HL register pair. These register pairs are commonly used to store memory addresses and other data.

The program counter is a 16-bit register that contains the memory address of the next instruction to be executed. The program counter is incremented after each instruction is executed, which allows the microprocessor to execute instructions in sequence.

The stack pointer is a 16-bit register that is used to manage the stack. The stack is a section of memory that is used to store data temporarily, such as subroutine addresses and other data. The stack pointer is used to keep track of the top of the stack.

The instruction register is an 8-bit register that contains the current instruction being executed. The instruction register is used by the microprocessor to decode and execute instructions.

The flags register is an 8-bit register that contains status flags that indicate the result of an arithmetic or logical operation. These flags include the carry flag, zero flag, sign flag, and parity flag. The carry flag is set when an arithmetic operation generates a carry, the zero flag is set when the result of an arithmetic or logical operation is zero, the sign flag is set when the result of an arithmetic or logical operation is negative, and the parity flag is set when the result of an arithmetic or logical operation has an even number of 1 bits.

The data bus is an 8-bit bus that is used to transfer data between the microprocessor and memory or other devices. The data bus is bidirectional, which means that it can be used to read data from memory or write data to memory.

The address bus is a 16-bit bus that is used to address memory and other devices. The address bus is used to select the memory location or device that the microprocessor wants to access.

The control bus is a set of signals that controls the operations of the microprocessor, including the read and write operations. The control bus includes signals such as the read signal, write signal, interrupt signal, and reset signal. The read signal is used to read data from memory or other devices, the write signal is used to write data to memory or other devices, the interrupt signal is used to signal the microprocessor that an interrupt has occurred, and the reset signal is used to reset the microprocessor to its initial state.

8085 is an 8-bit, general-purpose microprocessor. It consists of the following functional units:

Arithmetic and Logic Unit (ALU) :

It is used to perform mathematical operations like addition, multiplication, subtraction, division, decrement, increment, etc. Different operations are carried out in ALU: Logical operations, Bit-Shifting Operations, and Arithmetic Operations.

Flag Register:

It is an 8-bit register that stores either 0 or 1 depending upon which value is stored in the accumulator. Flag Register contains 8-bit out of which 5-bits are important and the rest of 3-bits are “don’t Care conditions”. The flag register is a dynamic register because after each operation to check whether the result is zero, positive or negative, whether there is any overflow occurred or not, or for comparison of two 8-bit numbers carry flag is checked. So for numerous operations to check the contents of the accumulator and from that contents if we want to check the behavior of given result then we can use Flag register to verify and check. So we can say that the flag register is a status register and it is used to check the status of the current operation which is being carried out by ALU.

Different Fields of Flag Register:

Parity Flag
Auxiliary Carry Flag

Accumulator:

Accumulator is used to perform I/O, arithmetic, and logical operations. It is connected to ALU and the internal data bus. The accumulator is the heart of the microprocessor because for all arithmetic operations Accumulator’s 8-bit pin will always there connected with ALU and in most-off times all the operations carried by different instructions will be stored in the accumulator after operation performance.

General Purpose Registers:

There are six general-purpose registers. These registers can hold 8-bit values. These 8-bit registers are B,C,D,E,H,L. These registers work as 16-bit registers when they work in pairs like B-C, D-E, and H-L. Here registers W and Z are reserved registers. We can’t use these registers in arithmetic operations. It is reserved for microprocessors for internal operations like swapping two 16-bit numbers. We know that to swap two numbers we need a third variable hence here W-Z register pair works as temporary registers and we can swap two 16-bit numbers using this pair.

Program Counter :

Program Counter holds the address value of the memory to the next instruction that is to be executed. It is a 16-bit register.

For Example: Suppose current value of Program Counter : [PC] = 4000H (It means that next executing instruction is at location 4000H.After fetching,program Counter(PC) always increments by +1 for fetching of next instruction.)

Stack Pointer :

It works like a stack. In stack, the content of the register is stored that is later used in the program. It is a 16-bit special register. The stack pointer is part of memory but it is part of Stack operations, unlike random memory access. Stack pointer works in a continuous and contiguous part of the memory. whereas Program Counter(PC) works in random memory locations. This pointer is very useful in stack-related operations like PUSH, POP, and nested CALL requests initiated by Microprocessor. It reserves the address of the most recent stack entry.

Temporary Register:

It is an 8-bit register that holds data values during arithmetic and logical operations.

Instruction register and decoder:

It is an 8-bit register that holds the instruction code that is being decoded. The instruction is fetched from the memory.

Timing and control unit:

The timing and control unit comes under the CPU section, and it controls the flow of data from the CPU to other devices. It is also used to control the operations performed by the microprocessor and the devices connected to it. There are certain timing and control signals like Control signals, DMA Signals, RESET signals and Status signals.

Interrupt control:

Whenever a microprocessor is executing the main program and if suddenly an interrupt occurs, the microprocessor shifts the control from the main program to process the incoming request. After the request is completed, the control goes back to the main program. There are 5 interrupt signals in 8085 microprocessors: INTR, TRAP, RST 7.5, RST 6.5, and RST 5.5.

Priorities of Interrupts: TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR

Address bus and data bus:

The data bus is bidirectional and carries the data which is to be stored. The address bus is unidirectional and carries the location where data is to be stored.

In the 8085 microprocessor, the address bus and data bus are two separate buses that are used for communication between the microprocessor and external devices.

The Address bus is used to transfer the memory address of the data that needs to be read or written. The address bus is a 16-bit bus, allowing the 8085 to access up to 65,536 memory locations.

The Data bus is used to transfer data between the microprocessor and external devices such as memory and I/O devices. The data bus is an 8-bit bus, allowing the 8085 to transfer 8-bit data at a time. The data bus can also be used for instruction fetch operations, where the microprocessor fetches the instruction code from memory and decodes it.

The combination of the address bus and data bus allows the 8085 to communicate with and control external devices, allowing it to execute its program and perform various operations.

Serial Input/output control:

It controls the serial data communication by using Serial input data and Serial output data.

Serial Input/Output control in the 8085 microprocessor refers to the communication of data between the microprocessor and external devices in a serial manner, i.e., one bit at a time. The 8085 has a serial I/O port (SID/SOD) for serial communication. The SID pin is used for serial input and the SOD pin is used for serial output. The timing and control of serial communication is managed by the 8085’s internal circuitry. The 8085 also has two special purpose registers, the Serial Control Register (SC) and the Serial Shift Register (SS), which are used to control and monitor the serial communication.

The flow of an Instruction Cycle in 8085 Architecture :

Execution starts with Program Counter. It starts program execution with the next address field. it fetches an instruction from the memory location pointed by Program Counter.
For address fetching from the memory, multiplexed address/data bus acts as an address bus and after fetching instruction this address bus will now acts as a data bus and extract data from the specified memory location and send this data on an 8-bit internal bus. For multiplexed address/data bus Address Latch Enable(ALE) Pin is used. If ALE = 1 (Multiplexed bus is Address Bus otherwise it acts as Data Bus).
After data fetching data will go into the Instruction Register it will store data fetched from memory and now data is ready for decoding so for this Instruction decoder register is used.
After that timing and control signal circuit comes into the picture. It sends control signals all over the microprocessor to tell the microprocessor whether the given instruction is for READ/WRITE and whether it is for MEMORY/I-O Device activity.
Hence according to timing and control signal pins, logical and arithmetic operations are performed and according to that data fetching from the different registers is done by a microprocessor, and mathematical operation is carried out by ALU. And according to operations Flag register changes dynamically.
With the help of Serial I/O data pin(SID or SOD Pins) we can send or receive input/output to external devices .in this way execution cycle is carried out.
While execution is going on if there is any interrupt detected then it will stop execution of the current process and Invoke Interrupt Service Routine (ISR) Function. Which will stop the current execution and do execution of the current occurred interrupt after that normal execution will be performed.

Uses of 8085 microprocessor :

The 8085 microprocessor is a versatile 8-bit microprocessor that has been used in a wide variety of applications, including:

Embedded Systems: The 8085 microprocessor is commonly used in embedded systems, such as industrial control systems, automotive electronics, and medical equipment.
Computer Peripherals: The 8085 microprocessor has been used in a variety of computer peripherals, such as printers, scanners, and disk drives.
Communication Systems: The 8085 microprocessor has been used in communication systems, such as modems and network interface cards.
Instrumentation and Control Systems: The 8085 microprocessor is commonly used in instrumentation and control systems, such as temperature and pressure controllers.
Home Appliances: The 8085 microprocessor is used in various home appliances, such as washing machines, refrigerators, and microwave ovens.
Educational Purposes: The 8085 microprocessor is also used for educational purposes, as it is an inexpensive and easily accessible microprocessor that is widely used in universities and technical schools.

Issues in 8085 microprocessor :

Here are some common issues with the 8085 microprocessor:

Overheating: The 8085 microprocessor can overheat if it is used for extended periods or if it is not cooled properly. Overheating can cause the microprocessor to malfunction or fail.
Power Supply Issues: The 8085 microprocessor requires a stable power supply for proper operation. Power supply issues such as voltage fluctuations, spikes, or drops can cause the microprocessor to malfunction.
Timing Issues: The 8085 microprocessor relies on accurate timing signals for proper operation. Timing issues such as clock signal instability, noise, or interference can cause the microprocessor to malfunction.
Memory Interface Issues: The 8085 microprocessor communicates with memory through its address and data buses. Memory interface issues such as faulty memory chips, loose connections, or address decoding errors can cause the microprocessor to malfunction.
Hardware Interface Issues: The 8085 microprocessor communicates with other devices through its input/output ports. Hardware interface issues such as faulty devices, incorrect wiring, or improper device selection can cause the microprocessor to malfunction.
Programming Issues: The 8085 microprocessor is programmed with machine language or assembly language instructions. Programming issues such as syntax errors, logic errors, or incorrect instruction sequences can cause the microprocessor to malfunction or produce incorrect results.
Research and development: The 8085 microprocessor is often used in research and development projects, where it can be used to develop and test new digital electronics and computer systems. Researchers and developers can use the microprocessor to prototype new systems and test their performance.
Retro computing: The 8085 microprocessor is still used by enthusiasts today for retro computing projects. Retro computing involves using older computer systems and technologies to explore the history of computing and gain a deeper understanding of how modern computing systems have evolved.

Reference :

“Microprocessor Architecture, Programming, and Applications with the 8085” by Ramesh S. Gaonkar – This book provides a comprehensive introduction to the architecture and programming of the 8085 microprocessor, along with examples and exercises.
“The 8085 Microprocessor: Architecture, Programming and Interfacing” by Udaya Kumar – This book provides an in-depth treatment of the architecture, programming, and interfacing of the 8085 microprocessor, with numerous examples and exercises.
“Introduction to Microprocessors and Microcontrollers” by John Crisp – This book provides an introduction to the architecture and programming of various microprocessors and microcontrollers, including the 8085.
Intel 8085 Microprocessor Data Sheet – This is the official data sheet for the 8085 microprocessor, which provides detailed information on the architecture, instruction set, and programming of the microprocessor.
Online resources such as tutorials, articles, and videos are also available on websites like tutorialspoint.com, electronicsforu.com, and YouTube.

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Customer Case Study: DataStax and Semantic Kernel

Sophia Lagerkrans-Pandey

Greg stachnick.

April 4th, 2024 0 0

Today we’ll dive into a customer case study from Datastax and their recent press release and announcement on the DataStax and Microsoft collaboration on RAG capabilities on DataStax Astra DB Thanks again to the DataStax team for their amazing partnership!

Microsoft and DataStax Simplify Building AI Agents with Legacy Apps and Data

In the ever-evolving landscape of artificial intelligence (AI) development, bridging the gap between legacy applications and cutting-edge AI technologies is a challenge for many enterprises. Companies often have hundreds or even thousands of existing applications that they want to bring into the AI world. Recognizing this challenge, Microsoft and DataStax have joined forces to simplify the process of building AI agents with legacy apps and data. Their latest partnership announcement combines AI development by enabling seamless integration of DataStax Astra DB with Microsoft’s Semantic Kernel.

Microsoft’s Semantic Kernel is an open-source SDK that helps solve this challenge, by making it easy to build generative AI agents that can call existing code. We’re excited to announce the new integration of Semantic Kernel and DataStax Astra DB that enables developers to build upon their current codebase more easily, vectorize the data, and build production-grade GenAI apps and AI agents that utilize the relevance and precision provided by retrieval-augmented generation (RAG).

What’s so cool about Semantic Kernel – shared by DataStax

Semantic Kernel is a GenAI/RAG application and agent orchestration framework in Microsoft’s stack of AI copilots and models. In many ways, it’s similar to LangChain and LlamaIndex, but with more focus on enabling intelligent agents. Semantic Kernel provides capabilities for managing contextual conversations including previous chats, prompt history, and conversations, as well as planners for multi-step functions and connections (plug-ins) for third-party APIs to enable RAG grounded in enterprise data (learn more about why RAG is critical to generating responses that aren’t only contextually accurate but also information-rich here ).

Another cool thing about Semantic Kernel is that prompts written for a Python version during app iteration can be used by the C# version for much faster execution at runtime. Semantic Kernel is also proven on Microsoft Azure for Copilot and has reference frameworks for developers to build their own scalable copilots with Azure.

Introducing the Astra DB Connector

DataStax has contributed the Astra DB connector in Python. This connector enables Astra DB to function as a vector database within Semantic Kernel. It’s a game-changer for developers building RAG applications that want to use Semantic Kernel’s unique framework features for contextual conversations or intelligent agents, or for those targeting the Microsoft AI and Azure ecosystem. The integration allows for the storage of embeddings and the performance of semantic searches with unprecedented ease.

By combining Semantic Kernel with Astra DB, developers can build powerful RAG applications with extended contextual conversation capabilities (such as managing chat and prompt histories) and multi-function or planner capabilities, on a globally scalable vector database proven to give more relevant and faster query responses.

A performance booster for Python developers

While this release will benefit a broad swath of the GenAI developer community, it’s of particular interest to those who work in the Microsoft/Azure ecosystem. By integrating Astra DB directly into Semantic Kernel, developers can now leverage Astra DB as a data source in their existing applications, streamlining the development process and enhancing application performance.

To add Astra DB support to a Semantic Kernel application, simply import the module and register the memory store:

The integration of Semantic Kernel and Astra DB extends beyond technical enhancements, paving the way for a range of business use cases from personalized customer service to intelligent product recommendations and beyond. It’s not just about making development easier; it’s about enabling the creation of more intelligent, responsive, and personalized AI applications that can transform industries.

For more information about this collaboration, visit the following links from DataStax:

DataStax and Microsoft Collaborate to Make it Easier to Build Enterprise Generative AI and RAG Applications with Legacy Data | DataStax
Announcing the New Astra DB and Microsoft Semantic Kernel Integration: Elevating Retrieval Augmented Generation | DataStax

Please reach out if you have any questions or feedback through our Semantic Kernel GitHub Discussion Channel . We look forward to hearing from you! We would also love your support, if you’ve enjoyed using Semantic Kernel, give us a star on GitHub .

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Sustainable, inclusive housing growth: A case study on Columbus, Ohio

Over the past two decades, the Columbus region has enjoyed outsize population and economic growth compared with leading peer cities and the US average. 1 In this article, “Columbus” refers to the Columbus metropolitan statistical area unless otherwise specified. See “Ohio Metropolitan Statistical Areas (MSAs),” Ohio Department of Job and Family Services, Office of Workforce Development, accessed June 22, 2023. Yet growth has come at a cost—specifically by outpacing the region’s supply of available housing. Home and rental prices have soared as stock has been depleted, making homeownership—and sometimes even having a roof over one’s head—increasingly out of reach for many people, particularly those from historically marginalized communities.

About the authors

This article is a collaborative effort by Brandon Carrus , Seth Myers , Brian Parro, Duwain Pinder , and Ben Safran, representing views from McKinsey’s Social Sector Practice.

In just this past decade, the increase in housing prices and rents has dramatically outpaced household income. Additionally, the region’s population of people experiencing homelessness (PEH) has grown faster than those of its US peers in recent years. The region’s challenges have a disproportionate impact on historically marginalized populations (such as Black and Hispanic residents), who have a dramatically lower likelihood of being a homeowner and a much higher likelihood of experiencing homelessness. Amid ongoing rapid growth, the need for affordable housing and support services for PEH will only continue to increase unless significant action is taken. 2 HUD defines affordable housing as “housing on which the occupant is paying no more than 30 percent of gross income for housing costs, including utilities.” See “Glossary of terms to affordable housing,” HUD, accessed June 22, 2023.

Columbus is a microcosm of the United States’ housing insecurity plight. While many major cities are receiving national press coverage for this issue, housing insecurity is a humanitarian challenge facing communities of all sizes across the country. The National Association for Home Builders estimates that about 70 percent of US households cannot afford a new home at the national median price. 3 NAHBNow , “Nearly 7 out of 10 households can’t afford a new median-priced home,” blog entry by National Association of Home Builders, February 15, 2022. In 2022, US home vacancy rates were at their lowest levels since 1987, 4 “Home vacancy rate for the United States,” US Census Bureau, retrieved from Federal Reserve Bank of St. Louis (FRED) June 22, 2023. and the country is estimated to have a shortage of 6.5 million housing units. 5 Anna Bahney, “The US housing market is short 6.5 million homes,” CNN, March 8, 2023. Renters are also facing increased pressure nationally: 23 percent spend at least half of their income on housing costs, 6 Katherine Schaeffer, “Key facts about housing affordability in the U.S.,” Pew Research Center, March 23, 2022. rendering them “severely rent burdened” as defined by the US Department of Housing and Urban Development (HUD). 7 “Rental burdens: Rethinking affordability measures,” PD&R Edge, accessed June 22, 2023.

As in many regions in the United States, the primary contributors to the housing shortage in Columbus are embedded within deeply vexing economic and social issues, including stagnating incomes, racial gaps in homeownership, and access to financing and services.

As Columbus charts a growth strategy for the decades ahead, addressing housing and homelessness will be an essential component in realizing the goal of prosperity for all. Today, Columbus is projected to have a shortage of as much as 110,000 housing units by 2032. 8 Vogt Strategic Insights, “Analysis of housing need for the Columbus region,” Building Industry Association of Central Ohio, August 30, 2022. Without an increase in the supply of housing, Columbus may struggle to continue on a growth trajectory. Specifically, we have identified four priority interventions designed to work in concert to increase housing stock, keep rents affordable, and help more people, including historically marginalized populations, access the housing market:

Tap into existing housing capacity potential. Public–private collaboration on policies can identify land available for housing either as underused property or as part of broader rezoning efforts to increase the supply of homes, which is a requirement for sustained economic growth.
Reduce the cost of new construction. Promising cost-reduction opportunities include simplifying the permit process and engaging builders with expertise in cost-effective construction methods.
Support homebuyers and renters. Local government and policy makers can expand resources and consider policies that support public- and private-sector initiatives to improve homeownership rates, assist with rental affordability, and reduce the risk of homelessness.
Prioritize tackling homelessness. Alleviating homelessness requires increasing awareness of currently available resources for PEH and expanding relief funds to assist residents with affordable housing, healthcare support, training for employment, and other resources critical to reducing homelessness.

Many local leaders are well aware of the challenges that can result from booming growth. The policy-neutral research presented in this article is intended to complement the work already under way by leaders in the city of Columbus and surrounding areas to inform decision making about the housing shortage, affordable housing, and homelessness. 9 For example, see Bonnie Meibers, “Columbus details plan to build, preserve and invest in inclusive affordable housing,” Columbus Business First , June 27, 2022; Bonnie Meibers, “Columbus City Council announces 12-part plan to combat affordable housing shortage,” Columbus Business First , March 16, 2023; Bonnie Meibers, “The Punch List: Columbus lays out new solutions to housing crisis,” Columbus Business First , October 24, 2022; Mark Ferenchik, “Worthington considering asking for $1.1M affordable housing bond issue on November ballot,” Columbus Dispatch , January 16, 2023. In the process, we believe the Columbus region’s approach to housing could both build on and inform the economic development strategies of other regions across the country—with successes offering a potential blueprint for progress.

The fastest-growing region in the Midwest

From 2000 to 2021, the Columbus Region’s population increased by a third, adding more than 500,000 people and becoming the fastest-growing metropolitan statistical area (MSA) in the Midwest. 10 “Resident population in Columbus, OH (MSA) [COLPOP],” US Census Bureau, retrieved from FRED April 7, 2023. Includes MSAs with populations greater than one million. Midwest defined as Illinois, Indiana, Iowa, Kansas, Michigan, Minnesota, Missouri, Ohio, Nebraska, North Dakota, South Dakota, and Wisconsin. See “Resident population in Columbus,” retrieved April 7, 2023; Factbook 2020 , City of Columbus, accessed June 22, 2023. In September 2022, Columbus was named the fifth-hottest housing market in the United States, driven by the speed of home sales and demand. 11 “CAGDP1 County and MSA gross domestic product (GDP) summary,” US Bureau of Economic Analysis, accessed May 12, 2023; “Table 1.1.6. Real Gross Domestic Product, Chained Dollars,” US Bureau of Economic Analysis, accessed May 12, 2023.

This growth was precipitated by, and continues to benefit from, the region’s mounting economic strength: from 2008 through 2021, Columbus outpaced national GDP growth by almost ten percentage points. 12 “Total gross domestic product for Columbus, OH (MSA) [NGMP18140],” US Bureau of Economic Analysis, retrieved from FRED June 23, 2023; “Gross domestic product [GDP],” US Bureau of Economic Analysis, retrieved from FRED June 23, 2023. Growth has also been bolstered by more-recent major commercial investments from a range of industries, including semiconductors, financial services, and biopharmaceuticals. 13 “Intel breaks ground in Ohio,” JobsOhio, accessed June 22, 2023; “Project announcements,” One Columbus, accessed June 22, 2023; “Western Alliance Bank expands into the Columbus Region, creating 150 new jobs at new technology hub,” One Columbus, January 9, 2023; “Discover plans to open a customer care center in Whitehall to bring high-quality jobs and enhance equity in the Columbus Region,” One Columbus, November 18, 2022.

Growing pains: Coping with rapid growth

The population influx has measurably strained Columbus’s residential real estate and rental markets, particularly for people of color. Increasing housing supply is a critical enabler for the region’s continued growth trajectory.

Increasing housing supply is a critical enabler for the region’s continued growth trajectory.

Rapidly rising home prices. Although the region remains relatively affordable compared with leading peers, home prices have skyrocketed in relation to incomes. Data from Zillow reveal that roughly a decade ago, the growth of median household incomes in Columbus and the value of the city’s “lower tier” housing stock began to diverge (Exhibit 1). In the ten years since then, lower-tier housing prices within the city’s boundaries increased at 1.9 times the growth of median household income—an unsustainable divergence. 14 Zillow Home Value Index (ZHVI) All Homes - Bottom Tier Time Series, accessed April 19, 2023. A cavalry in the form of new-housing construction may be slow to arrive: from 2004 to 2022, annual construction of new single-family homes in Columbus fell by 34 percent, and it has yet to return to pre-2004 levels. 15 “B19013 Median household income in the past 12 months,” ACS 5-Year Estimates 2016–21, American Community Survey, US Census Bureau. In fact, for every 100 net new jobs in the region, only 65 new housing permits were issued. 16 Analysis of housing need for the Columbus region , Vogt Strategic Insights, August 30, 2022.

Rent increases outpacing wage increases. Renters in Columbus have also seen a price surge.

Rent prices in Columbus increased by about 35 percent between December 2016 and December 2021, exceeding median household income growth in that period by 11 percentage points (Exhibit 2). As a result, by 2021, approximately 40 percent of renters in Columbus were spending more than 30 percent of their income on rent, meeting HUD’s definition of “rent burdened.” 17 “Gross rent as a percentage of household income,” 2021: ACS 5-Year Estimates, American Community Survey, US Census Bureau. And renters account for a significant percentage of residents: as of 2021, nearly 40 percent of total households in the metro area were rentals, which is comparable to other fast-growing US regions such as Austin (around 41 percent) and Miami (about 40 percent) but much higher than similar sized regions such as Pittsburgh (around 29 percent) and Indianapolis (about 32 percent). 18 “B25008 Total population in occupied housing units by tenure,” 2021: ACS 1-Year Estimates, American Community Survey, US Census Bureau.

More people experiencing homelessness.

Columbus outpaced its US peers in the growth of its PEH population from 2008 through 2022 (Exhibit 3), and early reports indicate homelessness was up 22 percent in January 2023 compared with January 2022. 19 “Columbus region leaders introduce new action on homelessness: Funding for programs and services introduced as data shows increase in homeless count,” Community Shelter Board, June 6, 2023. McKinsey research on homelessness in the Bay Area indicates that homelessness is a result of a range of disparate triggers, including economic issues (such as job loss, raised rent, or foreclosure), health factors (such as substance abuse or mental illness), and social factors (for example, incarceration or domestic violence). 20 For more, see “ The ongoing crisis of homelessness in the Bay Area: What’s working, what’s not ,” McKinsey, March 23, 2023. A brief but significant drop in the number of PEH in Columbus in 2021 is likely attributable to additional support during the pandemic (for example, eviction moratoriums and stimulus payments). Still, as of 2022, Columbus had the fastest-growing PEH population among its peers.

Columbus outpaced its US peers in the growth of its PEH population from 2008 through 2022, and early reports indicate homelessness was up 22 percent in January 2023 compared with January 2022.

Disproportionate effect on historically marginalized communities. The racial disparities that plague many leading US regions are also starkly apparent in Columbus. Some historically marginalized groups are less likely to be homeowners: one-third of the region’s Black households own their homes, compared with more than two-thirds of White households (Exhibit 4). Black household incomes in the region are also about 42 percent lower than those of White households. 21 “S1903 Median income in the past 12 months (in 2021 inflation-adjusted dollars),” 2021: ACS 1-Year Estimates, American Community Survey, US Census Bureau.

In addition, Black residents account for 16 percent of Columbus’s general population but 60 percent of the homeless population. 22 “DP05 ACS demographic and housing estimates,” 2021: ACS 5-Year Estimates Data Profiles, American Community Survey, US Census Bureau; “PIT and HIC data since 2007,” HUD Exchange, February 2023. And even when people in these communities have housing, Black households are almost five times more likely to be overcrowded (more than one occupant per room) than White households. 23 “B25014B Occupants per room (Black or African American alone householder),” 2021: ACS 5-Year Estimates, American Community Survey, US Census Bureau; “B25014A Occupants per room (White alone householder),” 2021: ACS 5-Year Estimates, American Community Survey, US Census Bureau. These disparate experiences in different communities are reflected in other metrics of financial and housing stability, including income and the ability to pass on generational wealth. 24 “B19013B Median household income in the past 12 months (in 2021 inflation-adjusted dollars) (Black or African American alone householder),” 2021: ACS 5-Year Estimates, American Community Survey, US Census Bureau; “B19013A Median household income in the past 12 months (in 2021 inflation-adjusted dollars) (White alone householder),” 2021: ACS 5-Year Estimates, American Community Survey, US Census Bureau; Jung Hyun Choi, Laurie Goodman, and Jun Zhu, Intergenerational homeownership: The impact of parental homeownership and wealth on young adults’ tenure choices , Urban Institute, October 2018.

These disproportionate effects have wide-ranging impact, including on overall economic growth. PolicyLink and the USC Equity Research Institute estimate that the racial gap in Columbus is costing the region’s economy $10 billion annually. 25 Erica Thompson and Mark Williams, “Racial inequities costs Columbus economy $10 billion a year, report finds,” Columbus Dispatch , updated May 12, 2022.

Four interventions to address Columbus’s housing challenges

Housing is a critical enabler for economic growth—and Columbus’s housing challenges are no secret. Local leaders, organizations, and partnerships have long worked to improve housing security directly. Advocates and organizations have all published research on housing and homelessness, including the Mid-Ohio Regional Planning Commission, the Coalition on Housing and Homelessness in Ohio, the Affordable Housing Trust for Columbus & Franklin County, the Center for Social Innovation, and the Community Shelter Board of Columbus. 26 Healthy Beginnings at Home: Final report , CelebrateOne and the Health Policy Institute of Ohio, June 2021; Regional Housing Strategy final report: Central Ohio , Mid-Ohio Regional Planning Commission, September 2020; Annual report 2021: Preserving, creating & facilitating , Affordable Housing Trust for Columbus and Franklin County, 2021; Columbus, Ohio: Initial findings from quantitative and qualitative research , Supporting Partnerships for Anti-Racist Communities (SPARC), Center for Social Innovation, May 2018. Yet the latest estimates show that the region could need as many as 110,000 housing units beyond the current run rate by 2032 to cover expected job growth. This would require more than doubling the construction rate, from around 8,300 units per year to as many as 19,300 per year. 27 Analysis of housing need for the Columbus region , Vogt Strategic Insights, August 30, 2022.

After reviewing the available research, examining the actions taken by other local governments, and drawing on our experience in the real estate and public sectors, we have identified four key interventions that can augment existing efforts to address Columbus’s housing challenge: tap into existing housing capacity potential, reduce the cost of new construction, support homebuyers and renters, and prioritize tackling homelessness.

Tap into existing housing capacity potential

Zoning regulates how land is used, where residential or commercial buildings may be constructed, and the density of new developments, making it a key lever in changing a city’s residential landscape. The city of Columbus spans 220 square miles of central Ohio, and it has 50 more square miles of single-family zoning than multifamily zoning. 28 Nicholas Julian, “Zoning in Columbus: Single-family vs. multifamily,” Ohio Housing Finance Agency, April 2, 2019; “QuickFacts: Columbus city, Ohio,” US Census Bureau, accessed June 22, 2023. Increasing density and creating housing “hot spots” are both potential options for Columbus to address current housing supply challenges.

Increased housing density. Zoning has a direct impact on housing density. In Washington, DC, for example, areas zoned for detached single-family units typically consist of up to 1,200 units per square mile, 29 Yesim Sayin, “Single-family zoning and neighborhood characteristics in the District of Columbia,” D.C. Policy Center, July 17, 2019. compared with up to 40,000 units per square mile in large multifamily buildings. But zoning in most US cities largely restricts higher-density homes. Three-quarters of the land in US cities is barred from development for anything other than detached single-family homes—and where multifamily buildings are allowed, height and lot size requirements hurt the economic calculus for development. 30 Jenny Schuetz, “To improve housing affordability, we need better alignment of zoning, taxes, and subsidies,” Brookings Institution, January 7, 2020. Specific zoning adjustments could contribute directly to closing the housing gap, not just in the city limits but also in the surrounding suburbs. For example, a recent analysis by the Columbus Dispatch found that zoning contributed to the lack of affordable housing options in Upper Arlington, New Albany, and suburbs in Delaware County. 31 Jim Weiker, “Columbus suburbs offer few affordable housing options,” Columbus Dispatch , May 4, 2023. High-density zoning can be a meaningful part of a community’s housing ecosystem to enable future growth.

‘Housing hot spots’ created by reusing and rezoning underused property. To help alleviate the shortage of homes in the near term, municipalities can also identify potentially high-impact housing areas by reviewing the zoning of properties that meet criteria for vacant or underutilized land, homes with room for more units, and more. This approach has been used elsewhere to great effect. An analysis of three counties in California found room for more than five million new units, 32 Jonathan Woetzel, Jan Mischke, Shannon Peloquin, and Daniel Weisfield, “ Closing California’s housing gap ,” McKinsey Global Institute, October 24, 2016. and separate efforts are under way in New York City and Los Angeles to rezone underused commercial zones for residential or mixed use—making more space available for housing construction without needing to expand a city’s footprint. 33 “Mayor Adams unveils recommendations to convert underused offices into homes,” City of New York, January 9, 2023; “Adequate sites for housing,” 2021–2029 Housing Element , Los Angeles City Planning, November 2021.

Reduce the cost of new construction

A priority for the Columbus region will be reducing the cost of new construction to accelerate the pace of development. Programs that accelerate construction, reduce permit fees, or otherwise defray development costs are common levers to help reduce the cost of affordable housing. Several approaches can be prioritized to address the challenges facing Columbus and other US regions.

Innovative, cost-saving construction techniques and builders. As in many areas of the United States, inflation drove up the cost of building materials, labor, and financing in Columbus by as much as 18 percent between 2021 and 2022. 34 “How much does it cost to build a house in Columbus?,” Home Builder Digest , accessed June 23, 2023. Innovative, low-cost approaches such as modular and prefabricated construction can help; in our experience, when applied at large scale, these techniques can reduce the cost of construction materials by up to 20 percent and decrease build time by 20 to 50 percent without sacrificing build quality. 35 Modular construction: From projects to products , McKinsey, June 18, 2019. This is especially true with projects featuring repeatable elements, such as schools and affordable housing.

Columbus, specifically, can establish itself as a center of excellence for modular and prefabricated construction by leveraging the region’s transportation network (such as railroads and highways) to efficiently transport modular units into the region. The region can further attract builders that use these construction techniques by offering tax incentives, investing in land and modular units at scale, reskilling the labor force, and streamlining the approval process to help drive affordable housing growth. These and other approaches could improve the economics for these kinds of construction projects almost immediately once implemented. For example, Portland, Oregon, made changes to its design review process to allow mixed-use and multifamily projects to go directly to the permit process, saving developers time and money by decreasing their financing costs. Local governments in the Columbus region can further improve the economics of housing development by producing and holding off-the-shelf design schematics that can easily be used by prospective housing-unit developers.

Reduced development costs. Identifying parcels of public land for housing development could defray the overall cost of new projects in addition to rezoning efforts. Some cities, including Copenhagen, London, New York City, and Stockholm, have established professional management of their publicly owned land, allowing them to identify suitable city-owned sites for affordable developments. 36 “ Affordable housing in Los Angeles: Delivering more—and doing it faster ”, McKinsey Global Institute, November 21, 2019.

Accelerating the construction permit process could help reduce lengthy permit timelines that both create delays and increase developers’ costs. Under Columbus’s permit approval system, new-construction permits can take six to nine months. In fast-growing metro areas elsewhere in the United States, permits can take as little as a few weeks—a disparity that the City of Columbus is reviewing as part of its longer-term affordable-housing initiatives. 37 Allen Henry, “Columbus to overhaul zoning code for first time in 70 years,” NBC4 WCMH-TV, October 20, 2021. The Affordable Housing Trust in Columbus has launched the Emerging Developers Accelerator Program to provide education and funding for minority developers. 38 Jim Weiker, “New program seeks to build ranks of minority and female developers,” Columbus Dispatch , updated May 18, 2022. Yet the holding costs due to the lengthy time horizon between initial plans and selling the first house keep many potential developers out of the business.

Reduced development finance costs and fees. Financing costs and government taxes tend to be a heavy burden on housing developers. Legal agreements and public financing tools, such as joint powers authorities (JPAs) and tax increment financing (TIF) programs, provide incentives for public and private partners to collaborate in the development of affordable housing. In instances where traditional incentives and subsidies are unable to produce the desired outcomes, JPAs enable the city, partnered with a developer, to issue bonds and use its property tax exemption to purchase a property or finance the creation of a new development process. As part of the acquisition process, the JPA agrees to restrict the rent of a set number of units in line with affordable-housing standards. This approach is unlike traditional affordable-housing projects in that long-term ownership rests with the city, with an option to purchase the property back from the JPA after a set period.

JPAs are eligible for significant tax exemptions on their properties, with the added benefit that these savings are passed on to renters. Bond financing can also be tax-exempt given that governmental bodies have the authority to issue tax-exempt bonds for facilities that provide a public benefit. 39 “Portantino bill creating regional affordable housing trust passes assembly local government committee,” Senator Anthony J. Portantino, California State Senate, June 9, 2022; Brennon Dixson et al., The ABCs of JPAs , SPUR and the Terner Center for Housing Innovation, June 2022. In California, the Burbank-Glendale-Pasadena Regional Housing Trust is leveraging these benefits to address barriers to building nearly 3,000 affordable-housing units in the region. 40 “Newsom signs Portantino bill creating Pasadena-Glendale-Burbank affordable housing trust,” Pasadena Star-News , August 24, 2022. The JPA will be allowed to request and receive private and state funding allocations, as well as authorize and issue bonds, to help finance affordable-housing projects.

As another option, TIF districts enable cities to freeze property tax revenue at current levels and use incremental tax revenue generated from a development to reimburse the developer’s costs over time. In 2018, for example, the City of Chicago approved TIF measures for The 78, a $7 billion mixed-use project to transform a former railroad property into 13 million square feet of residential, commercial, and institutional construction with a 20 percent commitment for affordable-housing units. According to plans, this TIF district will reimburse around $551 million in future increments for the construction of new infrastructure related to this project, including a new subway station, street improvements and extensions, and riverfront renovations. 41 “The 78,” Department of Planning and Development, City of Chicago, accessed June 23, 2023.

Support homebuyers and renters

In conjunction with initiatives that improve the supply of affordable housing, Columbus can explore approaches that improve an individual’s ability to pay for housing. The region can take these approaches in tandem to reduce the risk that demand will outpace supply and drive up prices on housing, making it even more unaffordable.

Homebuyer assistance from the public sector. Increasing investment in housing programs could help broaden the range of homes applicants can consider purchasing. For example, the City of Columbus’s Housing Division currently offers homebuyer assistance under its American Dream Downpayment Initiative (ADDI), which provides eligible first-time homebuyers with a loan of up to 6 percent of the purchase price (or up to $7,500) to put toward their down payment. 42 “American Dream Downpayment Initiative (ADDI) Program,” City of Columbus, accessed June 23, 2023. This loan is forgiven after five years if the resident meets certain requirements, including maintaining residency and not selling the property.

In Cleveland, Cuyahoga County’s Down Payment Assistance Program covers up to 10 percent of a home’s purchase price (or up to $16,600). 43 “Cuyahoga County Down Payment Assistance Program,” CHN Housing Capital, accessed June 23, 2023. This higher amount is especially significant given that the median sale price for a home in Columbus was $250,000 in December 2022, compared with $175,000 in Cuyahoga County and $115,000 in Cleveland itself. 44 “Columbus housing market,” Redfin, accessed June 23, 2023. The down payment program available in Cleveland provides greater assistance in real dollars in an area where those dollars can go further than in Columbus. Beyond affordable housing, assistance in the form of microloans and flexible funding programs have been shown to enable this transition. 45 Interval House, “How flexible funding can create stability and prevent homelessness,” Long Beach Community Foundation, accessed June 23, 2023.

Increasing the amount of assistance available could help broaden the options available to prospective homebuyers who could benefit from programs such as these, especially for historically marginalized communities that tend to have much lower rates of homeownership.

Rental assistance from the public sector. Some 54,000 households in the Columbus region are spending more than half their monthly incomes on rent, making rental assistance a cornerstone of the effort to improve housing affordability in the region. 46 Homeport website, US Department of Homeland Security and the United States Coast Guard, accessed June 23, 2023. Today, the State of Ohio and Franklin County have a number of rental assistance programs, including specific funds to help families, seniors, and veterans. 47 “Rent assistance providers,” Rentful, accessed June 23, 2023. Alternative programs, including flexible funding that allows for short-term, flexible financial assistance, could help stabilize individuals’ housing needs. 48 “How flexible funding can create stability,” accessed June 23, 2023.

Additionally, HUD subsidizes rent for low-income families. 49 A family’s income may not exceed 50 percent of the median income for the county or metropolitan area in which the family chooses to live, and 75 percent of vouchers must be provided to applicants whose income does not exceed 30 percent of the area median income. For more, see “Housing choice vouchers fact sheet,” HUD, accessed June 23, 2023. For fiscal year 2023, Columbus is allocated to receive approximately $12.7 million dollars in HUD funding for housing programs—approximately 16 percent more than Austin and 35 percent more than Denver 50 “Community Development Block Grant Program,” HUD, updated December 22, 2022; “HOME Investment Partnerships Program,” HUD, updated December 22, 2022; “Community planning and development formula program allocations for FY 2023,” HUD, updated May 3, 2023. —but the need for housing support exceeds the availability of funding. Columbus and Franklin County have also received more than $120 million combined due to the reallocation of unused federal COVID-19 relief funds to fight evictions, a majority of which is expected to go toward rent and utility assistance for low-income residents. 51 Bill Bush, “Columbus, Franklin County get over $120 million windfall in federal rental assistance,” Columbus Dispatch , May 8, 2023.

In addition, the Columbus City Council has made it illegal to deny a lease based on the source of a potential tenant’s rental payment—an effort to prevent landlords from denying leases to tenants using Section 8 subsidies. 52 Yilun Cheng, “Some landlords reject Section 8 renters despite Columbus law against discrimination,” Columbus Dispatch , February 8, 2022. The Columbus Metropolitan Housing Department has even offered cash incentives to landlords, and nonprofits have offered home upgrades in attempts to persuade more landlords to accept vouchers. 53 Jamilah Muhammad, “Central Ohio mother struggles to find homes accepting HUD vouchers,” Spectrum News 1, December 1, 2021. However, while these vouchers can effectively keep people housed, wait times to obtain them can be as long as 12 months. And about 30 percent of vouchers have expired over the past three years because participants could not find landlords in time. 54 “Some landlords reject Section 8 renters,” February 8, 2022. Streamlining the process from application to placement in subsidized housing could increase the impact of housing choice vouchers.

Potential interventions from the private sector

The private sector can take an active role in ensuring housing stability for both their employees and the communities where they operate by investing in and implementing sustainable-housing initiatives.

Three actions offer the potential for significant impact:

Offer housing assistance to employees. To build effective assistance plans, businesses can assess the specific needs of their employees and design targeted assistance, including employee housing, emergency housing assistance, down-payment assistance, and mortgage rate subsidies. Sugar Bowl Resort in California offers an array of affordable employee housing options near the resort. 1 “Employee housing,” Sugar Bowl Resort, accessed June 23, 2023. In Ohio, MetroHealth launched an employer-assisted housing program (EAHP), providing eligible employees $20,000 toward the purchase of a home near the hospital’s campus. 2 “MetroHealth System employees to receive up to $20,000 to buy a home near West 25th Street main campus,” MetroHealth System, June 24, 2019. Similarly, Habitat for Humanity in Dallas, Texas, started an EAHP with up to $13,000 in a forgivable loan for down payment assistance. 3 Lin Grensing-Pophal, “Employers begin offering home-buying support benefits,” SHRM, November 8, 2022.
Invest in increasing the supply of affordable housing. Businesses can invest in building new affordable-housing units in their communities. UnitedHealthcare has invested nearly $800 million to create approximately 19,000 housing units across the United States. 4 “Building health equity with $100 million in housing,” United HealthCare Services, July 6, 2022. In Columbus, Nationwide Children’s Hospital invests in the Healthy Neighborhoods Healthy Families initiative, which aims to increase access to and supply of affordable housing. And as businesses navigate a new hybrid phase of work and reassess their footprint needs, affordable housing is a powerful way to invest in and repurpose excess space. In Columbus, the owners of Continental Centre and PNC Tower have started converting office space to residential, creating hundreds of new rental units. 5 Dean Narciso, “Nationwide Children’s Hospital builds homes in South Linden with $4.2 million fund,” Columbus Dispatch , June 24, 2021.
Focus on affordable housing in site selection. Businesses can select sites for new locations based on availability of affordable housing, as well as give preference in requests for proposal (RFPs) to commercial real estate owners who invest in expanding affordable housing. 6 Bonnie Meibers, “Chase Tower in downtown Columbus could be converted from office to residential,” Columbus Business First , updated May 23, 2023.

Housing assistance from the private sector. Private-sector employers in Columbus and across the United States play a crucial role in helping employees maintain stable housing by providing appropriate compensation. However, simply paying employees a living wage may not be enough to ensure stable housing in the face of unexpected expenses or other financial difficulties. A recent Harvard Business Review article suggests that any investment in housing assistance can both attract new workers (a growing challenge for companies across the United States, with ten million unfilled jobs 55 “Total unfilled job vacancies for the United States,” Organisation for Economic Co-operation and Development, retrieved from FRED July 7, 2023. ) and increase the productivity of existing workers (for example, by creating a shorter commute or reducing stresses related to housing affordability). 56 Edward L. Glaeser and Atta Tarki, “What employers can do to address high housing costs,” Harvard Business Review , March 14, 2023. Other housing-security interventions—such as housing search and placement services, access to shower facilities, or even temporary hotel rooms—can support employees more quickly than local social services and also reduce employee turnover. Some corporate programs can provide immediate relief to recipients, while others can provide long-term benefits to at-risk individuals over the course of several years (see sidebar, “Potential interventions from the private sector”).

Any investment in housing assistance can both attract new workers and increase the productivity of existing workers.

Employers also can collaborate to provide a broader set of resources to employees. In Cleveland, for example, the Greater Living Circle offers financial assistance for home purchase, rent, and renovation projects for employees of nonprofit institutions in the Greater University Circle area, including in low-income neighborhoods. Such collaboration is also the goal of the Columbus Regional Housing Coalition, a task force focused on convening leaders across the region to address the region’s housing and homelessness challenges.

Prioritize tackling homelessness

Homelessness across the region served by the Columbus and Franklin County, Ohio Continuum of Care has increased by 33 percent in the past decade 57 The Columbus and Franklin County, Ohio Continuum of Care is the organization that oversees programs funded by HUD in the region. ; in January 2023, more than 2,300 people in the region were experiencing homelessness. 58 “Columbus region leaders introduce new action on homelessness,” June 6, 2023.

Improving awareness of available resources and expanding access to essential resources—such as healthcare, transitional housing, and training programs—can help alleviate challenges for PEH and reduce the homelessness rate across the region.

Improve awareness of existing resources. A recurring problem in approaches to homelessness is a lack of public awareness of resources available to PEH. This is especially a concern among people who have recently lost their source of housing, including young people (aged 18–24). Partnering with other organizations to increase awareness of and augment available resources can equip individuals with the means to self-resolve or seek help earlier. Even initiatives that partner with existing organizations can provide immediate relief. For example, in December 2022, the City of Columbus partnered with Columbus Coalition for the Homeless to launch an interactive map showing the locations of warming centers and homeless shelters to help individuals find places to keep warm in the winter months.

Expand essential resources to alleviate homelessness. Expanding access to essential resources will be necessary to combat the increase in homelessness. Health resources make it much more likely that PEH will remain housed after securing a more permanent living situation. For PEH who have health issues such as substance abuse or severe mental health disorders, long-term health-focused housing should be considered. Efforts that expand housing with easily available healthcare resources could provide both immediate and gradually increasing support in reducing chronic homelessness. These resources can be combined with existing techniques for ensuring PEH have the resources they need to secure permanent housing. Other innovative solutions such as alternatives to traditional security deposits and credit scores can support PEH who may not have enough savings for a security deposit or the credit history to be approved for a loan.

One emerging strategy is providing training to PEH by placing them in some form of transitional housing and helping them find employment so that they can remain housed. Portland, Oregon, and other cities have also amended zoning to allow for more homeless shelters and more flexible group living, while increasing access to resources PEH may need. 59 “Warming stations,” City of Columbus, accessed June 23, 2023; Lindsey Mills, “Columbus leaders, community partners launch interactive map for warming centers, homeless shelters,” WBNS-TV, December 19, 2022. In Columbus, the Community Shelter Board (CSB) serves thousands of people through programs to prevent and respond to homelessness, including partnering with landlords to create additional housing capacity for PEH and with the Homelessness Prevention Network to coordinate social services in the community for PEH. 60 “Major updates to the City’s housing-related zoning rules coming August 1,” City of Portland, Oregon, July 16, 2021.

As Columbus’s population continues to grow, stressors that come from growth need to be understood and mitigated head-on through innovative approaches. Through a focus on housing development, the region’s public, private, and civic leaders are seeking to improve housing security while supporting economic development. By setting clear goals to increase the overall housing supply, reduce the cost of new construction, provide support to improve housing affordability, and assist those who are currently experiencing homelessness, 61 Community Shelter Board website, accessed June 23, 2023. Columbus could make significant strides toward sustainable and inclusive growth, set an example for other regions, and ensure that all who wish to reside here can find a place of their own to call home.

Brandon Carrus is a senior partner in, and managing partner of, McKinsey’s Ohio office, where Seth Myers is a partner and Brian Parro is an associate partner; Duwain Pinder is a partner in the Ohio office and is a leader of the McKinsey Institute for Black Economic Mobility; Ben Safran is a partner in the Washington, DC, office.

The authors wish to thank Kyoka Allen, Charlie Baca, Laura Hempton, and Sarthak Soni for their contributions to this article.

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The 8086 microprocessor is an 8-bit/16-bit microprocessor designed by Intel in the late 1970s. It is the first member of the x86 family of microprocessors, which includes many popular CPUs used in personal computers. The architecture of the 8086 microprocessor is based on a complex instruction set computer (CISC) architecture, which means that ...
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