research papers on computer architecture

Efficient Large Scale DLRM Implementation on Heterogeneous Memory Systems

Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella High Performance Computing: 38th International Conference, ISC High Performance 2023.

HammerSim: A Tool to Model Rowhammer

Kaustav Goswami, Ayaz Akram, Hari Venugopalan, Jason Lowe-Power, Young Architect Workshop at ASPLOS 2023.

Validating gem5’s Memory Components

Mahyar Samani, Jason Lowe-Power, gem5 workshop at ISCA 2022.

Rethinking the Management Techniques in Emerging Memory Systems

Maryam Babaie, Ayaz Akram, Jason Lowe-Power MICRO 2022: The 8th CWIDCA Workshop.

Toward High-Fidelity Heterogeneous Memory System Modeling in gem5

Maryam Babaie, Ayaz Akram, Jason Lowe-Power ModSim 2022: Workshop on Modeling & Simulation of Systems and Applications

A Cycle-level Unified DRAM Cache Controller Model in gem5

Maryam Babaie, Ayaz Akram, Jason Lowe-Power ISCA 2022: The 4th gem5 Tutorial and User’s Workshop.

SoK: Limitations of Confidential Computing via TEEs for High-Performance Compute Systems

Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power. IEEE International Symposium on Secure and Private Execution Environment Design (SEED) 2022.

Modeling HBM2 Memory Controller

Ayaz Akram, Maryam Babaie, Wendy Elsasser, Jason Lowe-Power. The 4th gem5 Users’ Workshop associated with ISCA 2022.

LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads

Marjan Fariborz, Mahyar Samani, Pouya Fotouhi, Roberto Proietti, Il-min yi, Venkatesh Akella, Jason Lowe-Power, Samuel Palermo, S. J. Ben Yoo ISC-HPC 2022.

HTA: A Scalable High-Throughput Accelerator for Irregular HPC Workloads

Pouya Fotouhi, Marjan Fariborz, Roberto Proietti, Jason Lowe-Power, Venkatesh Akella, S. J. Ben Yoo ISC-HPC 2021.

Enabling Design Space Exploration for RISC-V Secure Compute Environments

Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power. Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021). With ISCA 2021.

Performance Analysis of Scientific Computing Workloads on General Purpose TEEs

Ayaz Akram, Anna Giannakou, Venkatesh Akella, Jason Lowe-Power, Sean Peisert. 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS ...

How to develop a bad research tool

Jason Lowe-Power. 2021 Workshop on Negative results, Opportunities, Perspectives, and Experiences (NOPE 2021). Held with ASPLOS. 2021

A Case Against Hardware Managed DRAM Caches for NVRAM based Systems

Best paper nominee Mark Hildebrand, Julian T. Angeles, Jason Lowe-Power, Venkatesh Akella 2021 IEEE International Symposium on Performance Analysis of System...

Enabling reproducible and agile full-system simulation

Best paper nominee Bobby R. Bruce, Ayaz Akram, Hoa Nguyen, Kyle Roarty, Mahyar Samani, Marjan Fariborz, Trivikram Reddy, Matthew D. Sinclair, Jason Lowe-Powe...

Investigating Hardware Caches for Terabyte-scale NVDIMMs

Julian T. Angeles, Mark Hildebrand, Venkatesh Akella, Jason Lowe-Power 12TH Annual Non-volatile Memories Workshop (NVMW 2021) 2021.

HCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems

Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew Farrens, Venkatesh Akella. ICPP 2020.

AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming

Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella 25th International Conference on Architectural Support for Programming Languages and Operating Systems (...

Using Trusted Execution Environments on High Performance Computing Platforms

Ayaz Akram and Anna Giannakou, Venkatesh Akella, Jason Lowe-Power, Sean Peisert Open-source Enclaves Workshop (OSEW 2019) 2019.

The Davis In-Order (DINO) CPU: A Teaching-focused RISC-V CPU Design

Jason Lowe-Power and Christopher Nitta Workshop on Computer Architecture Education (WCAE) 2019.

FlexCPU: A Configurable Out-of-Order CPU Abstraction

Bradley Wang, Ayaz Akram, Jason Lowe-Power ISPASS 2019.

Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP

Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew Farrens, and Venkatesh Akella. HiPC 2018.

Integrating Cycle Accurate Chisel Models with gem5’s System Simulation

Nima Ganjehloo, Jason Lowe-Power, Venkatesh Akella. CCC 2018.

A Case for Exposing Extra-Architectural State in the ISA

Jason Lowe-Power, Venkatesh Akella, Matthew K. Farrens, Samuel T. King, and Christopher J. Nitta. HASP Workshop with ISCA 2018.

Filtering Translation Bandwidth with Virtual Caching

Hongil Yoon, Jason Lowe-Power, Gurindar S. Sohi. ASPLOS 2018.

Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing

Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew Farrens, Venkatesh Akella. ICCD 2018.

When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data Workloads

Jason Lowe-Power, Mark D. Hill, David A. Wood. BPOE Workshop with ASPLOS 2016.

Border Control: Sandboxing Accelerators

Lena E. Olson, Jason Lowe-Power, Mark D. Hill, David A. Wood MICRO 2015.

Implications of Emerging 3D GPU Architecture on the Scan Primitive

Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, David A. Wood. SIGMOD Record 2015.

Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries

Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, David A. Wood. DaMoN (with SIGMOD) 2015.

gem5-gpu: A Heterogeneous CPU-GPU Simulator

Jason Power, Joel Hestness, Marc S. Orr, Mark D. Hill and David A. Wood. Computer Architecture Letters 2014.

Supporting x86-64 address translation for 100s of GPU lanes

Jason Power, Mark D. Hill,, David A. Wood. HPCA 2014.

Heterogeneous system coherence for integrated CPU-GPU systems

Jason Power, Arkaprava Basu, Junli Gu, Sooraj Puthoor, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, and David A. Wood MICRO 2013.

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• © 2022

Handbook of Computer Architecture

• Anupam Chattopadhyay   ORCID: https://orcid.org/0000-0002-8818-6983 0

Sch of Computer Science & Engineering, Nanyang Technological University, Singapore, Singapore

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• Reviews exhaustively the basic to the most advanced topics in computer architecture
• Includes in-depth study of design methodologies and tools for computer architectures
• Covers diverse types of architectures, ranging from ASICs, FPGAs to Multicores

5646 Accesses

8 Citations

7 Altmetric

• Table of contents

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Table of contents (33 entries)

Accelerator design with high-level synthesis.

• Christian Pilato, Stephanie Soldavini

Approximate Computing Architectures

• Muhammad Abdullah Hanif, Vojtech Mrazek, Muhammad Shafique

Architecture Description Languages

• Anupam Chattopadhyay, Zheng Wang, Grant Martin

Architectures for Machine Learning

• Yongkui Yang, Chao Chen, Zheng Wang

Architectures for Multimedia Processing: A Cross-Layer Perspective

• Muhammad Shafique, Bharath Srinivas Prabakaran

Architectures for Quantum Information Processing

• Suryansh Upadhyay, Mahabubul Alam, Swaroop Ghosh

Architectures for Self-Powered Edge Intelligence

• Amit Ranjan Trivedi, Jaeha Kung, Jong Hwan Ko

Bit-Level Model Checking

• Alexander Ivrii, Yakir Vizel

Coarse-Grained Reconfigurable Array (CGRA)

• Zhaoying Li, Dhananjaya Wijerathne, Tulika Mitra

Compute-in-Memory Architecture

• Hongwu Jiang, Shanshi Huang, Shimeng Yu

Dataflow Models of Computation for Programming Heterogeneous Multicores

• Jeronimo Castrillon, Karol Desnos, Andrés Goens, Christian Menard

Design and Tool Solutions for Monolithic Three-Dimensional Integrated Circuits

• Kyungwook Chang, Sung Kyu Lim

Design Automation Techniques for Microfluidic Biochips

• Xing Huang, Tung-Che Liang, Zhanwei Zhong, Tsung-Yi Ho, Krishnendu Chakrabarty

Fault Tolerant Architectures

• Siva Satyendra Sahoo, Anup Das, Akash Kumar

Field-Programmable Gate Array Architecture

• Andrew Boutros, Vaughn Betz

FPGA-Specific Compilers

• Nitish Srivastava, Gai Liu, Yi-Hsiang Lai, Zhiru Zhang

GPU Architecture

• Hyeran Jeon

High-Level Formal Equivalence

• Theo Drane, M. V. Achutha Kiran Kumar

Information Flow Verification

• Cynthia Sturton, Ryan Kastner

Methodologies for Design Space Exploration

• Andy D. Pimentel
• Single Core Processors
• Multicore Processors
• Application-Specific Processors
• Reconfigurable Architectures
• 3D Architectures
• Processor Design Flows
• Processor Programming Flows
• Security Verification
• Neuromorphic Computing
• Quantum Computing

Sch of Computer Science & Engineering, Nanyang Technological University, Singapore, Singapore

Anupam Chattopadhyay

Sayak  Ray , Intel, San Jose, California, USA

Book Title : Handbook of Computer Architecture

Editors : Anupam Chattopadhyay

DOI : https://doi.org/10.1007/978-981-15-6401-7

Publisher : Springer Singapore

eBook Packages : Springer Reference Engineering , Reference Module Computer Science and Engineering

eBook ISBN : 978-981-15-6401-7 Due: 19 May 2024

Number of Illustrations : 10 b/w illustrations, 10 illustrations in colour

Topics : Circuits and Systems , Processor Architectures , Electrical Engineering , Applications of Mathematics

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Nine CSE Research Papers in Computer Architecture Included in ISCA’s 25-Year Retrospective

By Kimberley Clementi

In commemoration of its 50th anniversary, the International Symposium on Computer Architecture (ISCA) has compiled a volume of memorable papers – a 25-Year Retrospective: 1996-2020 – to demonstrate the progression of research within computer architecture. The compilation of 98 research papers, culled from a pool of over a thousand submissions, included nine papers from UC San Diego’s Department of Computer Science and Engineering (CSE).

That means CSE faculty were involved in 10 percent of the selected papers.

Hadi Esmaeilzadeh had four research papers included in ISCA’s retrospective, as did CSE Professor Dean Tullsen. Jishen Zhao, an associate professor in the department, had one paper selected.

For more than two decades, their collective research has impacted the trajectory of computer architecture – spanning ground-breaking discoveries related to dark silicon, processors, simultaneous multithreading, and memory systems, enabling applications in machine learning, virtual reality, augmented reality, and artificial intelligence.

Papers for ISCA’s second commemorative volume were chosen by a team of referees to reflect the exciting evolution of computer architecture and share areas of potential growth. ISCA’s first volume, its 25 th anniversary retrospective, was published in 1998.

CSE faculty research included in ISCA@50 25-Year Retrospective: 1996-2020 :

Hadi Esmaeilzadeh – Bridging Computer Architecture and New Applications

Esmaeilzadeh, the inaugural holder of the Halıcıoğlu Chair in Computer Architecture at UC San Diego, is building the computer architecture that will enable AI and ML technologies of the future. He and his colleagues have focused on bridging the gap between the microarchitecture of processors and the increasing levels of performance required by computation-hungry applications. His highly-cited 2011 paper outlined this dilemma, while his more recent research proposes an architectural framework – dubbed Bit Fusion – developed to preserve accuracy while enabling ultra-power efficiency for deep learning.

Dark silicon and the end of multicore scaling

A reconfigurable fabric for accelerating large-scale datacenter services

General-purpose code acceleration with limited-precision analog computation

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network

Dean Tullsen – Standing the Test of Time

Widely considered one of computer architecture’s most influential researchers, CSE Professor Dean Tullsen has amassed five Test of Time Awards. This includes one for novel research on heterogenous multi-core architectures , which led to the design of many modern processors such as Qualcomm’s Snapdragon and Apple’s M1Pro and M1Max. Tullsen’s earlier contributions – including the introduction of simultaneous multithreading – were also deeply grounded in the issues of real, industry-leading processor design.

Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor

Selective value prediction

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling

Jishen Zhao – Creating Memorable Work in PIM

Zhao’s research stretches the boundary between computer architecture and system software, particularly in memory systems. Her 2016 ISCA paper showcases the possibilities that arise from combining emerging applications such as AI with technologies like ReRam, playing a crucial role in advancing research in Processing-in-Memory (PIM).

PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory

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EECS Alliance Roundup: 2023

Founded in 2019, The EECS Alliance program connects industry leading companies with EECS students for internships, post graduate employment, networking, and collaborations.  In 2023, it has grown to include over 30 organizations that have either joined the Alliance or participate in its flagship program, 6A.

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This ongoing listing of awards and recognitions won by our faculty is added to all year, beginning in September.

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